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F28M35H50B1RFPT Datasheet(PDF) 3 Page - Texas Instruments |
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F28M35H50B1RFPT Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 104 page  C3 RAM 8 KB (parity) C2 RAM 8 KB (parity) SECURE FLASH 512 KB (ECC) BOOT ROM 64 KB GPIO_MUX1 1.2V VREG 1.8V VREG SECURE C1 RAM 8 KB (ECC) SECURE C0 RAM 8 KB (ECC) AHB BUS APB BUS S0 - S7 SHARED RAM (parity) S0 8 KB S1 8 KB S2 8 KB S3 8 KB S4 8 KB S5 8 KB S6 8 KB S7 8 KB MTOC MSG RAM (parity) 2 KB CTOM MSG RAM (parity) 2 KB IPC INTER-PROCESSOR COMMUNICATIONS M3 SYSTEM BUS uDMA BUS L3 RAM 8 KB (parity) L2 RAM 8 KB (parity) SECURE FLASH 512 KB (ECC) BOOT ROM 64 KB SECURE L1 RAM 8 KB (ECC) SECURE L0 RAM 8 KB (ECC) GPIO_MUX1 M1 RAM 2 KB (ECC) M0 RAM 2 KB (ECC) C28 MEMORY BUS C28 DMA BUS 16-BIT PF2 32-BIT PF1 32-BIT PF3 INTER-PROCESSOR COMMUNICATIONS M3 BUS BRIDGE I-CODE BUS D-CODE BUS 66 PINS REGS ONLY TEMP SENS ADC_1 MODULE ADC_2 MODULE 4 COMP INPUTS 16/32-BIT PF0 ANALOG SUBSYSTEM RESETS NMI CLOCKS DEBUG RESETS NMI CLOCKS DEBUG 4 COMP INPUTS 10 ADC INPUTS 6 COMP OUTPUTS 10 ADC INPUTS C28 CPU C28 FPU C28 VCU PIE C28 DMA M3 uDMA M3 CPU NVIC MPU 6 COMP- ARATOR + DAC UNITS F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742B – JUNE 2011 – REVISED OCTOBER 2011 1.3 Functional Block Diagram Figure 1-1. Functional Block Diagram Copyright © 2011, Texas Instruments Incorporated F28M35x ( Concerto ™) MCUs 3 Submit Documentation Feedback |
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