Vishay Siliconix

SiC762CD

Document Number: 65727

S10-0275-Rev. A, 08-Feb-10

www.vishay.com

7

SMOD OPERATION DIAGRAM

PIN CONFIGURATION

Figure 4

DSBL

SMOD

PWM

GH

GL

VSW

Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top View

P2

P1

VSWH

P3

30 VSWH

29 VSWH

SMOD 1

BOOT 4

GH 6

PHASE 7

PIN DESCRIPTION

Pin Number

Symbol

Description

1

SMOD

Disable low side gate operation. Active low.

This will be the bias supply input for control IC (5 V).

IC bias supply and gate drive supply voltage (5 V).

4

BOOT

High side driver bootstrap voltage pin for external bootstrap capacitor.

5, 37, PAD1

6

GH

Gate signal output pin for high side MOSFET. Pin for monitoring.

7

PHASE

Return pin for the HS bootstrap capacitor. Connect a 0.1 µF ceramic capacitor from this pin to the boot pin (4).

8 to 14, PAD2

Input voltage for power stage. It is the drain of the high-side MOSFET.

15, 29 to 35,

PAD3

VSWH

It is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected

to an output inductor. All pins internally connected.

16 to 28

Power ground.

36

GL

Gate signal output pin for low side MOSFET. Pin for monitoring.

38

THDN

39

DSBL#

Disable pin. Active low.

40

PWM

PWM input logic signal. Compatible with Tristate controller function.