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OMAPL138BZCEA3E Datasheet(PDF) 5 Page - Texas Instruments |
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OMAPL138BZCEA3E Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 287 page  Switched Central Resource (SCR) BOOT ROM 256KB L2 RAM 32KB L1 RAM 32KB L1 Pgm 16KB I-Cache 16KB D-Cache AET 4KB ETB C674x™ DSP CPU ARM926EJ-S CPU With MMU DSP Subsystem ARM Subsystem JTAG Interface System Control Input Clock(s) 64KB ROM 8KB RAM (Vector Table) Power/Sleep Controller Pin Multiplexing PLL/Clock Generator w/OSC General- Purpose Timer (x4) Serial Interfaces Audio Ports McASP w/FIFO DMA Peripherals Display Internal Memory LCD Ctlr 128KB RAM External Memory Interfaces Connectivity EDMA3 (x2) Control Timers ePWM (x2) eCAP (x3) EMIFA(8b/16B) NAND/Flash 16b SDRAM DDR2/MDDR Controller RTC/ 32-kHz OSC I C (x2) 2 SPI (x2) UART (x3) McBSP (x2) Video VPIF Parallel Port uPP EMAC 10/100 (MII/RMII) MDIO USB1.1 OHCI Ctlr PHY USB2.0 OTG Ctlr PHY HPI MMC/SD (8b) (x2) SATA Customizable Interface PRU Subsystem OMAP-L138 www.ti.com SPRS586C – JUNE 2009 – REVISED MAY 2011 1.3 Functional Block Diagram (1) Note: Not all peripherals are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2009–2011, Texas Instruments Incorporated OMAP-L138 C6-Integra ™ DSP+ARM® Processor 5 Submit Documentation Feedback Product Folder Link(s): OMAP-L138 |
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