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SI9913DY Datasheet(PDF) 7 Page - Vishay Siliconix |
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SI9913DY Datasheet(HTML) 7 Page - Vishay Siliconix |
7 / 9 page Si9913 Vishay Siliconix Document Number: 71343 S-40133—Rev. B, 16-Feb-04 www.vishay.com 7 Bootstrap Supply Operation (see Functional Block Diagram) The power to drive the high-side MOSFET (Q2) gate comes from the bootstrap capacitor (CBOOT). This capacitor charges through D1 during the time when the low-side MOSFET is on (VS is at GND potential ), and then provides the necessary charge to turn on the high-side MOSFET. CBOOT should be sized to be greater than ten times the high-side MOSFET gate capacitance, and large enough to supply the bootstrap current (IBOOT) during the high-side on time, without significant voltage droop. Synchronous Enable The synchronous enable pin serves to enable and disable the drive to the low-side MOSFET gate. With SYN high, the low-side MOSFET is driven on and off in antiphase with the high-side MOSFET to form a synchronous rectifier. This improves efficiency at high load currents because the flyback current is carried by the MOSFET, thus eliminating the diode drop. With SYN low, the low-side MOSFET is held off all the time. This is particularly useful for discontinuous operation under light load or pulse skipping mode, where there is a long off time, because it prevents current flowing back from the output to ground during the off time. Layout Considerations There are a few critical layout considerations for these parts. Firstly, the IC must be decoupled as closely as possible to the power pins. Secondly the IC should be placed physically close to the high- and low-side MOSFETs it is driving. The major consideration is that the MOSFET gates must be charged or discharged in a few nanoseconds, and the peak current to do this is of the order of 1 A. This current must flow from the decoupling and bootstrap capacitors to the IC, and from the output driver pin to the MOSFET gate, returning from the MOSFET source to the IC. The aim of the layout is to reduce the parasitic inductance of these current paths as much as possible. This is accomplished by making these traces as short as possible, and also running trace and its current return path adjacent to each other. APPLICATIONS FIGURE 1. Typical Applications Schematic Circuit Used to Obtain Typical Rising and Falling Switching Waveforms 8 6 7 5 1 3 2 4 OUTH GND IN SYN VS BOOT VDD OUTL U1 Si9913 +5 V C2 0.1 mF PWM IN GND 1 mF C5 C1 0.1 mF Enable 4 4 Q1 Si4412 Q2 Si4412 +VDC L1 15 mH 0.1 mF C3 15 mF C4 GND + GND RLOAD |
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