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SI5908DC Datasheet(PDF) 8 Page - Vishay Siliconix |
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SI5908DC Datasheet(HTML) 8 Page - Vishay Siliconix |
8 / 10 page AN812 Vishay Siliconix www.vishay.com 2 Document Number: 71127 12-Dec-03 Front of Board Back of Board FIGURE 3. vishay.com ChipFETr THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 30_C/W typical, 40_C/W maximum for the dual device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the dual SO-8 package RQjf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical RQja for the dual-channel 1206-8 ChipFET is 90_C/W steady state, identical to the SO-8. Maximum ratings are 110_C/W for both the 1206-8 and the SO-8. Both packages have comparable thermal performance on the 1” square pcb footprint with the 1206-8 dual package having a quarter of the body area, a significant factor when considering board area. Testing To aid comparison further, Figure 4 illustrates ChipFET 1206-8 dual thermal performance on two different board sizes and three different pad patterns.The results display the thermal performance out to steady state and produce a graphic account on how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RQja for the Dual 1206-8 ChipFET are : 1) Minimum recommended pad pattern (see Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 185_C/W 2) The evaluation board with the pad pattern described on Figure 3. 128_C/W 3) Industry standard 1” square pcb with maximum copper both sides. 90_C/W The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 57_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 38_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square PCB. Time (Secs) FIGURE 4. Dual 1206-8 ChipFET 0 1 200 40 80 100 1000 120 10 10-1 10-2 10-3 10-4 10-5 1” Square PCB Dual EVB Min. Footprint 160 SUMMARY The thermal results for the dual-channel 1206-8 ChipFET package display identical power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. ASSOCIATED DOCUMENT 1206-8 ChipFET Single Thermal performance, AN811, (http://www.vishay.com/doc?71126). |
Similar Part No. - SI5908DC_10 |
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Similar Description - SI5908DC_10 |
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