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SI4724 Datasheet(PDF) 4 Page - Vishay Siliconix |
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SI4724 Datasheet(HTML) 4 Page - Vishay Siliconix |
4 / 11 page www.vishay.com 4 Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 Vishay Siliconix Si4724 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION CIRCUIT PIN CONFIGURATION Figure 1. MOSFET Drive Circuitry with Break-Before- Make Si4724 CBOOT CBOOT D1 S1 D2 S2 VDD SYNC EN IN GND + VOUT GND DC-DC Controller 0 V to 30 V 5 V GND Q1 Q2 Power Up Sequence: Ensure VDD is within spec before allowing IN or SYNC EN to be set high. Power Down Sequence: Ensure IN and SYNC EN are low before turning VDD off. 13 SO-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 Top View D1 S1 D1 S1 GND CBOOT IN VDD SYNC EN S2 S2 D2 D2 D2 S2 D2 Ordering Information: Si4724CY-T1 Si4724CY-T1-E3 (Lead (Pb)-free) TRUTH TABLE Sync EN CLK Q1 Q2 HH ON OFF HL OFF ON LH ON OFF LL OFF OFF PIN DESCRIPTION Pin Number Symbol Description 1, 2 D1 Highside MOSFET Drain 3 GND Ground 4 IN Input Logic Signal 5 SYNC EN Synchronous Enable 6, 7, 8 S2 Lowside MOSFET Source 9, 10, 11, 12 D2 Lowside MOSFET Drain 13 VDD Logic Supply, decoupling to GND with a cap is strongly recommended. 14 CBOOT Bootstrap Capacitor for Upper MOSFET 15, 16 S1 Highside MOSFET Source |
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