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MAX9856 Datasheet(PDF) 20 Page - Maxim Integrated Products |
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MAX9856 Datasheet(HTML) 20 Page - Maxim Integrated Products |
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20 / 46 page  Low-Power Audio CODEC with DirectDrive Headphone Amplifiers 20 ______________________________________________________________________________________ Status Registers Status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. The status register bits are cleared upon a read operation of the status register and are set the next time the event occurs. Table 2 lists the status registers bit location and description. REG B7 B6 B5 B4 B3 B2 B1 B0 0x00 CLD SLD ULK JKMIC HPOCL HPOCR JDET GPI 0x01 LSNS JKSNS HSDETL HSDETR JSDET Table 2. Status Registers Bit Location BIT FUNCTION CLD Clip Detect Flag. Indicates that a signal has become clipped in the ADC. SLD Slew-Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. ULK Digital PLL Unlock Flag. Indicates that the digital audio PLL for the DAC or ADC has become unlocked and digital signal data is not reliable. JKMIC Jack Microphone Flag. Indicates JACKSNS has been pulled up to the MICBIAS voltage. The microphone bias must be enabled for this bit to function properly. HPOCL/ HPOCR Headphone Output Left/Right Current Overload Flags. Indicate that the headphone output amplifiers have exceeded the rated current. JDET Headset Configuration Change Flag. Indicates a change in JKMIC, LSNS, or JKSNS. GPI GPI State. Indicates the state of LRCLK_A when configured as a general-purpose input. LSNS Headphone Sense. LSNS is set when the internal pullup current forces the voltage at HPL to exceed AVDD - 0.4V. This indicates headphone jack insertion or removal has occurred. HPMODE must be set to 00 and JDETEN set to 1 for this bit to function. JKSNS Jack Sense. JKSNS is set when the internal pullup current forces the voltage on JACKSNS to exceed AVDD - 0.4V. This indicates jack insertion or removal has occurred. JDETEN must be set for this bit to function. Load Impedance Sense. Indicates the approximate load connected to HPR, HPL, or JACKSNS. These bits are updated once each time the appropriate EN bits are set high and cause an undefeatable hardware interrupt. BITS HEADPHONE OR JACKSNS LOAD 00 200 Ω < load < open 01 50 Ω < load < 200Ω 10 0 < load < 50 Ω HSDETL, HSDETR, JSDET 11 Idle state Status Register Bit Description |
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