DS1216 SmartWatch RAM/SmartWatch ROM

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DETAILED DESCRIPTION

The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600-mil-wide DIP sockets with a

built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source.

The sockets provide an NV RAM solution for memory sized from 2K x 8 to 512K x 8 with package sizes

from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to

problems associated with memory volatility and uses a common energy source to maintain time and date.

The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A

key feature of the SmartWatch is that the watch function remains transparent to the RAM. The

lithium energy source is automatically switched on and write protection is unconditionally enabled to

prevent loss of watch and RAM data.

Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM

for RAM and watch control. All other pins are passed straight through to the socket receptacle.

The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,

hours, days, date, months, and years. The date at the end of the month is automatically adjusted for

months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either

24-hour or 12-hour format with an AM/PM indicator.

OPERATION

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of

64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on

DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and

either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is

disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC

registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC

registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low

during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match

sequence.

PATTERN MATCH—RAM

Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control

of chip enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory

location using the CE and OE control of the SmartWatch starts the pattern recognition sequence by

moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are

executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain

access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,

the write cycles generated to gain access to the SmartWatch are also writing data to a location in the

mated RAM. The preferred way to manage this requirement is to set aside just one address location in

RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the

64-bit comparison register. If a match is found, the pointer increments to the next location of the