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71M6521FE Datasheet(PDF) 44 Page - Maxim Integrated Products |
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71M6521FE Datasheet(HTML) 44 Page - Maxim Integrated Products |
44 / 107 page 71M6521DE/DH/FE Data Sheet Page: 44 of 107 Rev 2 Three-Wire EEPROM Interface A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 58. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits. Control Bit Name Read/Write Description 7 WFR W Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence. This bit is ignored if HiZ=0. 6 BUSY R Asserted while serial data bus is busy. When the BUSY bit falls, an INT5 interrupt occurs. 5 HiZ W Indicates that the SD signal is to made high impedance immediately after the last SCK rising edge. 4 RD W Indicates that EEDATA is to be filled with data from EEPROM. 3-0 CNT[3:0] W Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data will be read MSB first, and right justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent MSB first to EEPROM, shifted out of EEDATA’s MSB. If CNT is zero, SDATA will simply obey the HiZ bit. Table 58: EECTRL bits for 3-wire interface The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state. Figure 9: 3-Wire Interface. Write Command, HiZ=0. Figure 10: 3-Wire Interface. Write Command, HiZ=1 SCLK (output) BUSY (bit) CNT Cycles (6 shown) SDATA (output) Write -- No HiZ D2 D3 D4 D5 D6 D7 EECTRL Byte Written INT5 SDATA output Z (LoZ) CNT Cycles (6 shown) Write -- With HiZ INT5 EECTRL Byte Written SCLK (output) BUSY (bit) SDATA (output) D2 D3 D4 D5 D6 D7 (HiZ) (LoZ) SDATA output Z |
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