Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

LV25400W_0712 Datasheet(PDF) 34 Page - Sanyo Semicon Device

Part No. LV25400W_0712
Description  For Automotive Applications DSP Tuner Front End
Download  42 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  SANYO [Sanyo Semicon Device]
Homepage  http://www.ssdc-jp.com/eng/
Logo 

LV25400W_0712 Datasheet(HTML) 34 Page - Sanyo Semicon Device

Zoom Inzoom in Zoom Outzoom out
 34 / 42 page
background image
LV25400W
No.A0633-34/42
Continued from preceding page.
No.
Control block/data
Description
Related data
(11)
2.7V REG
ADJ
REG_ADJ0
REG_ADJ1
• Adjusts the 2.7 V regulator
2.7V REG ADJ
0 0
0 1
1 0
1 1
-23mV
(Center value)
+23mV
+64mV
(12)
Crystal oscillator selection
XS0, XS1
• Selects the crystal element.
XS1
XS0
X’tal OSC
0
0
1
1
0
1
0
1
4.5MHz
Illegal value
Illegal value
Illegal value
(13)
HD (wide) IF AGC amplifier
variation correction bits
ADJ_W0
ADJ_W1
ADJ_W2
ADJ_W3
• Corrects for sample-to-sample variations in the IF AGC amplifier gain
Amount of correction : ±5 dB
4 bit
(14)
DO pin control data (2)
IL0, IL1
• Controls the DO pin output
DO pin control data (2)
IL1
IL0
IN
0
0
1
1
0
1
0
1
Open
The I3 pin state (unused)
The I2 pin state (unused)
The I1 pin state (unused)
Since there are no connected pins in the current product, the open setting must be
used.
(15)
DO pin control data (1)
ULD
DT0, DT1
• Determines the DO pin output.
DO pin control data (1)
ULD
IL0
DT0
DO pin
0
0
1
1
0
1
0
1
0
1
0
1
Low when not locked.
Monitor 1 (unused)
Monitor 2 (unused)
(See DO control (2))
1
1
1
1
0
0
1
1
0
1
0
1
Open
Monitor 1 (unused)
Monitor 2 (unused)
(See DO control (2))
The following item (5) must also be set when monitoring the unlock detection signal.
UL0, UL1
(16)
Unlock state detection data
UL0, UL1
• Selects the phase error (øE) detection width used to judge the PLL locked state.
If a phase error in excess of the øE detection width from the table below occurs, the
PLL is seen as being in the unlocked state.
When the PLL is seen as being unlocked, the detection pin (DO) is set low.
UL1
UL0
φE detection width
Detection pin output
0
0
1
1
0
1
0
1
Stopped
0
±0.5
µs
±1
µs
Open
φE is output directly
φE is delayed by 1 to 2 ms.
φE is delayed by 1 to 2 ms.
ULD
DT0, DT1
Continued on next page.
Delay
Unlock state output
1 to 2ms
DO
φE


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn