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LV24230LS Datasheet(PDF) 8 Page - Sanyo Semicon Device |
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LV24230LS Datasheet(HTML) 8 Page - Sanyo Semicon Device |
8 / 17 page LV24230LS No.A1989-8/17 Digital interface specification (interface specification : reference) (1). Characteristics of SDA and SCL bus line relative to the I2C bus interface Parameter Symbol Standard-mode High_Speed-mode unit min max min max SCL clock frequency FSCL 0 100 0 400 kHz Fall time of both SDA and SCL Tf 300 20+0.1Cb 300 ns Rise time of both SDA and SCL Tr 1000 20+0.1Cb 300 ns High time of SCL THIGH 4.0 0.6 μs Low time of SCL TLOW 4.7 1.3 μs Hold time of STAT condition THD ; STA 4.0 0.6 μs Hold time of Data THD ; DAT 03.45 0 0.9 μs Set-up time of STAT condition TSU ; STA 4.7 0.6 μs Set-up time of STOP condition TSU ; STO 4.0 0.6 μs Set-up time of Data TSU ; DAT 250 100 ns Bus free time between a STOP and TBUF 4.7 1.3 μs Capacitivie load for each bus line Cb 400 400 pF *Cb = Total capacitance of one bus line (2). Register map (On Register Map) Following is Sub address map of LV24230LS. Each register becomes 8-bit constitution. Address Register Name Mode Remark 00h CHIP_ID R/W Chip ID 02h RADIO_STAT R Status of Radio Station 0Bh RFCAP R/W RF Cap bank 0Dh RADIO_CTRL1 R/W Radio Control 1 0Eh RADIO_CTRL2 R/W Radio Control 2 0Fh RADIO_CTRL3 R/W Radio Control 3 10h TNPL R Tune Position Low 11h TNPH_STAT R Tune Position High and Status 19h REF_CLK_PRS R/W Reference clock pre-scalar 1Ah REF_CLK_DIV R/W Reference clock divider 1Bh REF_CLK_OFF R/W Reference clock offset 1Dh SCN_CTRL R/W Scan control 1Eh TARGET_VAL_L R/W Target value Low 1Fh TARGET_VAL_H R/W Target value High R : Read only register R/W : Read and Write register SCL SDA THIGH Repeated START TSU;STA THD;DAT TSU;DAT THD;STA TLOW Tr START Condition Tf Tf Tr |
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