LV8111V

Continued from preceding page.

Pin No.

Pin name

Function

Equivalent circuit

22

HB

Hall element bias current pin.

Goes ON when the S/S pin is in a start state.

Goes OFF when the S/S pin is in an stopped state.

22

VREG

23

24

25

26

27

28

IN1+

IN1−

IN2+

IN2−

IN3+

IN3−

Hall amplifier input pin.

A high level state of logic is recognized when IN+ > IN−.

In reverse case is a low-level state.

The input amplitude of 100mVp-p or more (differential) is

desirable in the Hall sensor inputs.

If noise on the Hall inputs is a problem, that noise must be

excluded by inserting capacitors across the inputs.

25

VREG

500

Ω

500

Ω

26

24

28

27

23

29

SUB

Frame ground pin. This pin is connected with the GND2 pin.

30

GND2

Ground pin of the output circuit block.

32

34

36

OUT3

OUT2

OUT1

Output pin.

As for PWM, Duty control is executed on the upper- side

FET.

38

RF

Source pin of output MOSFET (lower-side).

Connect a low resistance (Rf) between this pin and GND.

32

VCC

34 36

38

39

RFS

Output current detection pin.

Connect to RF pin.

39

5k

Ω

VREG

40

VCC2

Power supply pin.

Connect a capacitor between this pin and GND for

stabilization.

41

VCC1

Power supply pin for control.

42

VG

Charge pump output pin (Power supply for the upper side

FET gate).

Connect a capacitor between this pin and VCC.

43

44

CP1

CP2

Pin to connect a capacitor for charge pump.

Connect a capacitor between CP1 and CP2.

VCC

44

500

Ω

42

43

100

Ω

No.A1416-10/13