LC875G32A/24A/16A/08A

No.8299-3/23

AD Converter : 12-bits/8-bits×12-channels

• 12-bits/8-bits AD converter selectable

• Automatic reference voltage generation controllable

PWM : Multifrequency 12-bit PWM×2-channels

Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)

• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)

Watchdog Timer

• External RC watchdog timer

• Interrupt and reset signals selectable

Interrupts

• 22 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of

the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4

4

0001BH

H or L

INT3/INT5/base timer

5

00023H

H or L

T0H

6

0002BH

H or L

T1L/T1H

7

00033H

H or L

SIO0/UART1 receive

8

0003BH

H or L

SIO1/UART1 transmit

9

00043H

H or L

ADC/T6/T7

10

0004BH

H or L

Port 0/T4/T5/PWM0, PWM1

• Priority Level: X > H > L

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

• 16-bits×8-bits

(5 tCYC execution time)

• 24-bits×16-bits

(12 tCYC execution time)

• 16-bits÷8-bits

(8 tCYC execution time)

• 24-bits÷16-bits

(12 tCYC execution time)

Oscillation Circuits

• RC oscillation circuit (internal):

For system clock

• CF oscillation circuit:

For system clock, with internal Rf

• Crystal oscillation circuit:

For low-speed system clock, with internal Rf

• Frequency variable RC oscillation circuit (internal): For system clock

System Clock Divider Function

• Can run on low current.

• The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs

(at a main clock rate of 10MHz).