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HT46R01B-1 Datasheet(PDF) 52 Page - Holtek Semiconductor Inc |
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HT46R01B-1 Datasheet(HTML) 52 Page - Holtek Semiconductor Inc |
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52 / 71 page  HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Rev.1.00 52 June 9, 2011 ¨ HT48R01B-1/HT48R01N-1 Bit 76543210 Name ¾¾ TBF ¾¾¾ TBE ¾ R/W ¾¾ R/W ¾¾¾ R/W ¾ POR ¾¾ 0 ¾¾¾ 0 ¾ Bit 7~6 unimplemented, read as ²0² Bit 5 TBF: Time Base event interrupt request flag 0: inactive 1: active Bit 4~2 unimplemented, read as ²0² Bit 1 TBE: Time base event interrupt enable 0: disable 1: enable Bit 0 unimplemented, read as ²0² Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the timer in- terrupt request flag, TnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. A/D Converter Interrupt The HT46R01B-1 and HT46R01N-1 devices include an A/D interrupt. For an A/D interrupt to occur, the global in- terrupt enable bit EMI and the corresponding interrupt enable bit ADE must be first set. An actual A/D interrupt will take place when the A/D converter request flag ADF is set, a situation that will occur when an A/D conversion process has completed. When the interrupt is enabled, the stack is not full and an A/D conversion process fin- ishes execution, a subroutine call to the relevant A/D in- terrupt vector, will take place. When the interrupt is serviced, the A/D interrupt request flag ADF will be auto- matically reset and the EMI bit will be automatically cleared to disable other interrupts. As this interrupt vec- tor location is shared with other interrupts, to be effec- tive it must be selected via configuration option. Time Base Interrupt For a time base interrupt to occur the global interrupt en- able bit EMI and the corresponding interrupt enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bits, a requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the ²CALL subroutine ² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well con- trolled, the original control sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Sleep Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. |
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