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DG401DY-T1-E3 Datasheet(PDF) 2 Page - Vishay Siliconix |
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DG401DY-T1-E3 Datasheet(HTML) 2 Page - Vishay Siliconix |
2 / 17 page www.vishay.com 2 Document Number: 70049 S09-2561-Rev. I, 30-Nov-09 Vishay Siliconix DG401, DG403, DG405 FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Two SPDT Switches per Package Logic "0" ≤ 0.8 V Logic "1" ≥ 2.4 V Two DPST Switches per Package Logic "0" ≤ 0.8 V Logic "1" ≥ 2.4 V DG403 D1 S1 NC Dual-In-Line and SOIC IN1 D3 V- S3 GND S4 VL D4 V+ NC IN2 D2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Top View D3 NC V- S2 S3 IN2 GND NC NC D2 NC NC S4 S1 VL IN1 D4 NC V+ D1 Key Top View LCC 910 11 12 13 4 5 6 7 8 1 2 319 20 14 15 16 17 18 DG403 TRUTH TABLE Logic SW1, SW2 SW3, SW4 0 OFF ON 1ON OFF DG405 D1 S1 NC Dual-In-Line and SOIC IN1 D3 V- S3 GND S4 VL D4 V+ NC IN2 D2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Top View D3 NC V- S2 S3 IN2 GND NC NC D2 NC NC S4 S1 VL IN1 D4 NC V+ D1 Key Top View LCC 910 11 12 13 4 5 6 7 8 1 2 319 20 14 15 16 17 18 DG405 TRUTH TABLE Logic Switch 0 OFF 1ON |
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