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LNK408LG Datasheet(PDF) 4 Page - Power Integrations, Inc.

Part No. LNK408LG
Description  LinkSwitch-PH LED Driver IC Family
Download  20 Pages
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Manufacturer  POWERINT [Power Integrations, Inc.]
Direct Link  http://www.powerint.com
Logo POWERINT - Power Integrations, Inc.

LNK408LG Datasheet(HTML) 4 Page - Power Integrations, Inc.

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Rev. D 08/11
Figure 6.
5.9 V Regulator/Shunt Voltage Clamp
The internal 5.9 V regulator charges the bypass capacitor
connected to the BYPASS pin to 5.9 V by drawing a current
from the voltage on the DRAIN pin whenever the power FET is
off. The BYPASS pin is the internal supply voltage node. When
the power FET is on, the device operates from the energy
stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows LinkSwitch-PH
to operate continuously from current it takes from the DRAIN
pin. A bypass capacitor value of 10 or 100 mF is sufficient for
both high frequency decoupling and energy storage. In
addition, there is a 6.4 V shunt regulator clamping the BYPASS
pin at 6.4 V when current is provided to the BYPASS pin
through an external resistor. This facilitates powering of
LinkSwitch-PH externally through a bias winding to increase
operating efficiency. It is recommended that the BYPASS pin is
supplied current from the bias winding for normal operation.
In the event of an open-loop fault (open FEEDBACK pin resistor
or broken path to feedback winding), output short-circuits or an
overload condition the controller enters into the auto-restart
mode. The controller annunciates both short-circuit and
open-loop conditions once the FEEDBACK pin current falls
below the I
FB(AR) threshold after the soft-start period. To
minimize the power dissipation under this fault condition the
shutdown/auto-restart circuit turns the power supply on (same
as the soft-start period) and off at an auto-restart duty cycle of
typically DC
AR for as long as the fault condition persists. If the
fault is removed during the auto-restart off-time, the power
supply will remain in auto-restart until the full off-time count is
completed. Special consideration must be made to appropriately
size the output capacitor to ensure that after the soft-start
period (t
SOFT) the FEEDBACK pin current is above the IFB(AR)
threshold to ensure successful power-supply start-up.
After the soft-start time period, auto-restart is activated only
when the FEEDBACK pin current falls below I
Over-Current Protection
The current limit circuit senses the current in the power FET.
When this current exceeds the internal threshold (I
LIMIT), the power
FET is turned off for the remainder of that cycle. A leading edge
blanking circuit inhibits the current limit comparator for a short
time (t
LEB) after the power FET is turned on. This leading edge
blanking time has been set so that current spikes caused by
capacitance and rectifier reverse recovery will not cause
premature termination of the power FET conduction.
Line Under/Overvoltage Protection
This device includes both line under- and overvoltage detection
to limit the minimum start-up and maximum operating voltage
detected through the VOLTAGE MONITOR pin. An external peak
detector consisting of a diode and capacitor are required to
provide input line peak voltage to the VOLTAGE MONITOR pin
through a resistor. At power up, I
UV+ keeps the LinkSwitch-PH
off until the input line voltage reaches the undervoltage threshold.
At power down, I
UV- prevents restart attempts after the output
goes out of regulation.
The same resistor used for UV also sets line overvoltage (OV)
shutdown threshold which, once exceeded, forces the
LinkSwitch-PH to stop switching (after completion of the current
switching cycle). Once the line voltage returns to normal, the
device resumes normal operation. A small amount of hysteresis
is provided on the OV threshold to prevent noise triggering.
When the power FET is off, the rectified DC high voltage surge
capability is increased to the voltage rating of the power FET
(725 V), due to the absence of the reflected voltage and leakage
spikes on the drain.
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die
temperature. The threshold is set at 142 °C typical with a 75 °C
hysteresis. When the die temperature rises above this threshold
(142 °C) the power FET is disabled and remains disabled until
the die temperature falls by 75 °C, at which point the power FET
is re-enabled.
Safe Operating Area (SOA) Protection
The device also features a safe operating area (SOA) protection
mode which disables FET switching for 40 cycles in the event
the peak switch current reaches the ILIMIT threshold and the
switch on-time is less than t
ON(SOA). This protection mode
protects the device under short-circuited LED conditions and at
start-up during the soft-start period when auto-restart protection
is inhibited. The SOA protection mode remains active in normal

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