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FM25C160B-GTR Datasheet(PDF) 8 Page - Ramtron International Corporation |
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FM25C160B-GTR Datasheet(HTML) 8 Page - Ramtron International Corporation |
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8 / 13 page  FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 8 of 13 Figure 9. Memory Write Figure 10. Memory Read Endurance Internally, a F-RAM operates with a read and restore mechanism. Therefore, endurance cycles are applied for each access: read or write. The F-RAM architecture is based on an array of rows and columns. Each access causes a cycle for an entire row. In the FM25C160B, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, F-RAM read and write endurance is effectively unlimited at the 20MHz clock speed. Even at 2000 accesses per second to the same row, 15 years time will elapse before 10 12 endurance cycles occur. |
Similar Part No. - FM25C160B-GTR |
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Similar Description - FM25C160B-GTR |
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