DRV8302

www.ti.com

SLES267

– AUGUST 2011

RECOMMENDED OPERATING CONDITIONS

MIN

TYP MAX

UNITS

PVDD1

DC supply voltage PVDD1 for normal operation

Relative to PGND

8

60

V

PVDD2

DC supply voltage PVDD2 for buck converter

3.5

60

V

External capacitance on AVDD pin (ceramic cap) 20% tolerance

1

µF

External capacitance on DVDD pin (ceramic cap) 20% tolerance

1

µF

External capacitance on GVDD pin (ceramic cap) 20% tolerance

2.2

µF

Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance

22

nF

Bootstrap cap (ceramic cap)

100

nF

Input current of digital pins when EN_GATE is high

100

µA

Input current of digital pins when EN_GATE is low

1

µA

Maximum capacitance on digital input pin

10

pF

Maximum output capacitance on outputs of shunt amplifier

20

pF

Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150k

Ω) with a

0

150

k

Ω

linear approximation.

FAULT pin sink current. Open-drain

V = 0.4 V

2

mA

OCTW pin sink current. Open-drain

V = 0.4 V

2

mA

External voltage reference voltage for current shunt amplifiers

2

6

V

Qg(TOT) = 25 nC or total 30 mA gate

Operating switching frequency of gate driver

200

kHz

drive average current

Ambient temperature

–40

125

°C

ELECTRICAL CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL

High input threshold

2

V

Low input threshold

0.8

V

Internal pull down resistor for EN_GATE

100

k

Ω

Internal pull down resistor for high side PWMs

EN_GATE high

100

k

Ω

(INH_A, INH_B, and INH_C)

Internal pull down resistor for low side PWMs

EN_GATE high

100

k

Ω

(INL_A, INL_B, and INL_C)

Internal pull down resistor for M_PWM

EN_GATE high

100

k

Ω

Internal pull down resistor for M_OC

EN_GATE high

100

k

Ω

Internal pull down resistor for DC_CAL

EN_GATE high

100

k

Ω

OUTPUT PINS: FAULT AND OCTW

Low output threshold

0.4

V

External 47 k

Ω pull up resistor connected to

High output threshold

2.4

V

3-5.5 V

Leakage Current on Open Drain Pins When

1

µA

Logic High (FAULT and OCTW)

Copyright

© 2011, Texas Instruments Incorporated

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Product Folder Link(s): DRV8302