Electronic Components Datasheet Search |
|
ADUM2251 Datasheet(PDF) 10 Page - Analog Devices |
|
ADUM2251 Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page ADuM2250/ADuM2251 Data Sheet Rev. A | Page 10 of 16 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION The ADuM2250/ADuM2251 interface on each side to I2C sig- nals. Internally, the bidirectional I2C signals are split into two unidirectional channels communicating in opposite directions via dedicated iCoupler isolation channels. One channel of each pair (the Side 1 input of each I/O pin in Figure 6) implements a special input buffer and output driver that can differentiate between externally generated inputs and its own output signals. It only transfers externally generated input signals to the corresponding Side 2 data or clock pin. Both the Side 1 and the Side 2 I2C pins are designed to interface to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low on either side causes the corresponding I/O pin across the coupler to be pulled low enough to comply with the logic low threshold requirements of other I2C devices on the bus. Bus contention and latch-up is avoided by guaranteeing that the input low threshold at SDA1 or SCL1 is at least 50 mV less than the output low signal at the same pin. This prevents an output logic low at Side 1 being transmitted back to Side 2 and pulling down the I2C bus by latching the state. Because the Side 2 logic levels/thresholds and drive capabilities comply fully with standard I2C values, multiple ADuM2250/ ADuM2251 devices connected to a bus by their Side 2 pins can communicate with each other and with other devices having I2C compatibility as shown in Figure 7. Note the distinction between I2C compatibility and I2C compliance. I2C compatibility refers to situations in which the logic levels or drive capability of a component do not necessarily meet the requirements of the I2C specification but still allow the com- ponent to communicate with an I2C-compliant device. I2C compliance refers to situations in which the logic levels and drive capability of a component fully meet the requirements of the I2C specification. Because the Side 1 pin has a modified output level/input thresh- old, Side 1 of the ADuM2250/ADuM2251 can only communicate with devices fully compliant with the I2C standard. In other words, Side 2 of the ADuM2250/ADuM2251 is I2C-compliant while Side 1 is only I2C-compatible. The Side 1 I/O pins must not be connected to other I2C buffers that implement a similar scheme of dual I/O threshold detection. This latch-up prevention scheme is implemented in several popular I2C level shifting and bus extension products currently available from Analog Devices and other manufac- turers. Care should be taken to review the data sheet of potential I2C bus buffering products to ensure that only one buffer on a bus segment implements a dual threshold scheme. A bus segment is a portion of the I2C bus that is isolated from other portions of the bus by galvanic isolation, bus extenders, or level shifting buffers. Table 11 shows how multiple ADuM2250/ ADuM2251 components can coexist on a bus as long as two Side 1 buffers are not connected to the same bus segment. Table 11. ADuM225x Buffer Compatibility Side 1 Side 2 Side 1 No Yes Side 2 Yes Yes The output logic low levels are independent of the VDD1 and VDD2 voltages. The input logic low threshold at Side 1 is also independent of VDD1. However, the input logic low threshold at Side 2 is designed to be at 0.3 VDD2, consistent with I2C require- ments. The Side 1 and Side 2 I/O pins have open-collector outputs whose high levels are set via pull-up resistors to their respective supply voltages. DECODE ENCODE ENCODE DECODE DECODE ENCODE ENCODE DECODE GND1 NC VDD1 NC SDA1 SCL1 NC GND1 GND2 NC VDD2 NC SDA2 SCL2 NC GND2 8 7 5 6 4 3 2 1 12 11 13 14 15 16 10 ADuM2250 SYMBOL INDICATES A DUAL THRESHOLD INPUT BUFFER. NC = NO CONNECT 9 Figure 6. ADuM2250 Block Diagram Figure 7 shows a typical application circuit including the pull-up resistors required for both Side 1 and Side 2 busses. Bypass capacitors of between 0.1 pF and 0.01 pF are required between VDD1 to GND1 and VDD2 to GND2. The 200 Ω resistor shown in Figure 7 is required for latch-up immunity if the ambient temperature can be between 105°C and 125°C. VDD1 OPTIONAL 200Ω SDA1 SCK1 GND1 VDD2 SDA2 SCK2 GND2 8 7 5 6 4 3 2 1 9 12 11 13 14 15 16 10 ADuM2250 µCPU OR SECONDARY BUS SEGMENT I2C BUS Figure 7. Typical Isolated I2C Interface Using ADuM2250 |
Similar Part No. - ADUM2251 |
|
Similar Description - ADUM2251 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |