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GS4901B Datasheet(PDF) 11 Page - Gennum Corporation |
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GS4901B Datasheet(HTML) 11 Page - Gennum Corporation |
11 / 102 page GS4901B/GS4900B SD Clock and Timing Generator with GENLOCK Data Sheet 37703 - 4 December 2009 11 of 102 17 VSYNC Non Synchronous Input REFERENCE SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. The VSYNC external reference signal is applied to this pin by the application layer. When the GS4901B/GS4900B is operating in Genlock mode, the device senses the polarity of the VSYNC input automatically, and references to the leading edge. This signal must adhere to one of the 36 defined video standards supported by the device. In this mode of operation, the VSYNC input provides a vertical scanning reference signal. The VSYNC signal may have analog timing, such as from a sync separator, or may be digital such as from an SDI deserializer. Section 1.4 on page 19 describes the 36 video formats recognized by the GS4901B/GS4900B. 18, 31, 38, 50, 62 IO_VDD – Power Supply Most positive power supply connection for the digital I/O signals. Connect to either +1.8V DC or +3.3V DC. NOTE: All five IO_VDD pins must be powered by the same voltage. 19 FSYNC Non Synchronous Input REFERENCE SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. The FSYNC external reference signal is applied to this pin by the application layer. The first field is defined as the field in which the first broad pulse (also known as serration) is in the first half of a line. The FSYNC signal should be set HIGH during the first field for sync-based references. Then this signal must adhere to one of the 36 defined video standards supported by the device. In this mode of operation, the FSYNC input provides an odd/even field input reference. The FSYNC signal may have analog timing, such as from a sync separator, or may be digital such as from an SDI deserializer. Section 1.4 on page 19 describes the 36 video formats recognized by the GS4901B/GS4900B. For blanking-based references, the FSYNC signal should be set HIGH during the second field. NOTE: If the input reference format does not include an F sync signal, this pin should be held LOW. 27, 25, 24, 23, 22, 21 VID_STD[5:0] Non Synchronous Input CONTROL SIGNAL INPUTS Signal levels are LVCMOS/LVTTL compatible. Video Standard Select. Used to select the desired video format for video clock and timing signal generation. 4 different video sample clocks, as well as 9 different video format timing signal outputs may be selected using these pins. NOTE: The VID_STD[5:4] pins should be grounded by the application layer since these pins are not required to select output video standards 1 to 10. For details on the supported video standards and video clock frequency selection, please see Section 1.4 on page 19. 26, 44 CORE_VDD – Power Supply Most positive power supply connection for the digital core. Connect to +1.8V DC. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
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