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HMC628LP4 Datasheet(PDF) 8 Page - Hittite Microwave Corporation
HITTITE [Hittite Microwave Corporation]
HMC628LP4 Datasheet(HTML) 8 Page - Hittite Microwave Corporation
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For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or firstname.lastname@example.org
Serial Control Interface
(Direct Parallel Mode & Latched Parallel Mode)
The HMC628LP4(E) contains a 3-wire SPI compatible digital interface (DATA, CLK, LE). It is activated when P/S
is kept high. The 5-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires
clean transitions. Standard logic families work well. If mechanical switches were used, sufficient debouncing should
be provided. When LE is high, 5-bit data in the serial input register is transferred to the attenuator. When LE is high
CLK is masked to prevent data transition during output loading.
When P/S is low, 3-wire SPI interface inputs (DATA, CLK, LE) are disabled and serial input register is loaded
asynchronously with parallel digital inputs (B0-B4). When Le is high, 5-bit parallel data is transferred to the attenuator.
For all modes of operations, attenuation state will stay constant while LE is kept low.
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable)
must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in
the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired
states the LE is pulsed. See timing diagram above for reference.
(Latched Parallel Mode)
HMC628LP4 / 628LP4E
BiCMOS MMIC 5-Bit DIGITAL
VARIABLE GAIN AMPLIFIER, 50 - 800 MHz
Min. serial period, t
Control set-up time, t
Control hold-time, t
LE Set up-time, t
Min. LE pulse width, t
Min LE pulse spacing, t
Serial clock hold-time from LE, t
Hold Time, t
Latch Enable Minimum Width, t
Setup Time, t
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