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MC74HCT573A Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MC74HCT573A
Description  Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC74HCT573A Datasheet(HTML) 3 Page - Motorola, Inc

   
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MC74HCT573A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Sb l
P
Guaranteed Limit
Ui
Symbol
Parameter
– 55 to
25
_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Q
(Figures 1 and 5)
30
38
45
ns
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
30
38
45
ns
TPLZ,
TPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
tTZL,
tTZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
tTLH,
tTHL
Maximum Output Transition Time, any Output
(Figures 1 and 5)
12
15
18
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
C
P
Di
i
i
C
i
(P
E
bl d O
)*
Typical @ 25
°C, VCC = 5.0 V
F
CPD
Power Dissipation Capacitance (Per Enabled Output)*
48
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Sb l
P
Fi
Guaranteed Limit
Ui
Sb l
P
Fi
– 55 to 25
_C
v 85_C
v 125_C
Ui
Symbol
Parameter
Fig.
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
4
10
13
15
ns
th
Minimum Hold Time, Latch Enable to Input D
4
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
1
500
500
500
ns


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