MC74HCT273A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Sb l

P

Fi

Guaranteed Limit

Ui

Symbol

Parameter

Fig.

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

1, 4

30

24

20

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock to Q

1, 4

25

28

35

ns

tPHL

Maximum Propagation Delay, Reset to Q

2, 4

25

28

35

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

1, 5

18

20

22

ns

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

C

PDi

i

i

C

i

(P

G

)*

Typical @ 25

°C, VCC = 5.0 V

F

CPD

Power Dissipation Capacitance (Per Gate)*

30

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Sb l

P

Fi

Guaranteed Limit

Ui

Sb l

P

Fi

– 55 to 25

_C

v 85_C

v 125_C

Ui

Symbol

Parameter

Fig.

Min

Max

Min

Max

Min

Max

Unit

tsu

Minimum Setup Time, Data to Clock

3

10

12

15

ns

th

Minimum Hold Time, Clock to Data

3

3.0

3.0

3.0

ns

trec

Minimum Recovery Time, Set or Reset Inactive to Clock

2

5.0

5.0

5.0

ns

tw

Minimum Pulse Width, Clock

1

12

15

18

ns

tw

Minimum Pulse Width, Set or Reset

2

12

15

18

ns

tr, tf

Maximum Input Rise and Fall Times

1

500

500

500

ns