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IDT75K52134 Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT75K52134
Description  4.5M and 9M Network Search Engine (NSE) with LA-1 Interface
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT75K52134 Datasheet(HTML) 1 Page - Integrated Device Technology

  IDT75K52134_05 Datasheet HTML 1Page - Integrated Device Technology  
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1
JANUARY 2003
DSC-6070/00
 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
QDR™ - Quad Data Rate (Trademark of Cypress, IDT, Micron, NEC and Samsung.)
All brands or products are the trademarks or registered trademarks of their
respective owners.
Product
Brief
IDT75K52134
IDT75K62134
4.5M and 9M Network
Search Engine (NSE)
with LA-1 Interface
Introduction
As part of the IDT IP Co-Processor product family, IDT delivers high
performance, feature-rich, easy-to-use, Network Search Engine (NSE)
products. Using CAM (Content Addressable Memory) technology, IDT
NSEproductsacceleratesearchfunctionsforAccessControlLists(ACL),
FlowCaching,andforwardingtoimproveperformanceinnextgeneration
networkingequipment.
NSE Features
128K x 72 (9M) or 64K x 72 (4.5M) Data and Mask cells
Full Ternary Content Addressable Memory
AdvancedDatabaseManagement
-
SelectableDatabases
-
Programmable Width per Database
-
Lookup widths from 32 to 576 bits
-
Only the selected Database is powered
LookupInstructions
-
Standard Lookup
-
Multi-HitLookup
-
Multi-DatabaseLookup
-
Re-Issue Multi-Database Lookup
Maintenance Features
-
Aging
-
Multi Hit Invalidate
-
Learn per Database
Multi-Context support
Pool of (72-bit) Global Mask Registers (shared across contexts)
In-Band Control and Management
Assoicated Data SRAM is supported through a glue-less ZBT®
interface
Lowest Power per Application
Synchronous Pipeline Operation
Boundary Scan JTAG Interface
1.2V Core Supply
1.5V HSTL I/O Supply
2.5V I/O Supply for ZBT® Associated Data SRAM
35mm x 35mm BGA Package
Device Description
TheNSEwithasingleLA-1 interfaceisintendedtoworkwithanyNPU
having a LA-1 look aside interface. Multiple devices including the LA-1
NSEcanbeconnectedtothesameLA-1interface. EachLA-1NSEdevice
may be point-to-point expanded up to eight NSE devices.
External Interfaces
The following external interfaces are supported by the LA-1 NSE device
SingleLA-1NPUinterface
-
LA-1 Clock Frequency up to 250 MHz
-
Supports LA-1 burst of 2
-
Echo clocks supported (CQ,
CQ)
Point-to-PointCascadingInterface
-
Up to eight NSEs can be cascaded using this scheme
Associated Data SRAM with standard ZBT® Interface
Boundary Scan JTAG Interface (IEEE 1149.1)
Figure 1.0 LA-1 NSE External Interfaces
6070 drw04aa
QDR
Read
Control
Logic
QDR
Write
Control
Logic
ZBT
Interface
Cascade
Interface
JTAG Interface
256K x 36 Full
Ternary Content
Addressable Memory
To request the full datasheet, please contact your local
IDT Sales Representative or call 1-800-345-7015


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