PC MAIN CLOCK

1484E—07/07/11

ICS9LPRS525

PC MAIN CLOCK

6

NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

AC Electrical Characteristics - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

Rising Edge Slew Rate

tSLR

Averaging on

2.5

4

V/ns

2, 3

Falling Edge Slew Rate

tFLR

Averaging on

2.5

4

V/ns

2, 3

Slew Rate Variation

tSLVAR

Averaging on

20

%

1, 10

Differential Voltage Swing

VSWING

Averaging off

300

mV

2

Crossing Point Voltage

VXABS

Averaging off

300

550

mV

1,4,5

Crossing Point Variation

VXABSVAR

Averaging off

140

mV

1,4,9

Maximum Output Voltage

VHIGH

Averaging off

1150

mV

1,7

Minimum Output Voltage

VLOW

Averaging off

-300

mV

1,8

Duty Cycle

DCYC

Averaging on

45

55

%

2

CPU[1:0] Skew

CPUSKEW10

Differential Measurement

100

ps

1

CPU[2_ITP:0] Skew

CPUSKEW20

Differential Measurement

150

ps

1

SRC[10:0] Skew

SRCSKEW

Differential Measurement

3000

ps

1,6

induced modulation by setting C_cross_delta to be smaller than V_Cross absolute

NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

meets Clock# falling. The median cross point is used to calculate the voltage

Clock Jitter Specs - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

CPU Jitter - Cycle to Cycle

CPUJC2C

Differential Measurement

85

ps1

SRC Jitter - Cycle to Cycle

SRCJC2C

Differential Measurement

85

ps1

DOT Jitter - Cycle to Cycle

DOTJC2C

Differential Measurement

250

ps

1

NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver