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STM32F407IE Datasheet(PDF) 65 Page - STMicroelectronics

Part # STM32F407IE
Description  USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Download  154 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F407IE Datasheet(HTML) 65 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Electrical characteristics
Doc ID 022152 Rev 1
65/154
Table 17.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM (1)(2)
Symbol
Parameter
Conditions
fHCLK
Typ
Max(3)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current in
Run mode
External clock(4), all
peripherals enabled(5)
168 MHz
86.8
TBD
TBD
mA
144 MHz
67
TBD
TBD
120 MHz
56.2
TBD
TBD
90 MHz
43.5
TBD
TBD
60 MHz
29.7
TBD
TBD
30 MHz
16.3
TBD
TBD
25 MHz
12.4
TBD
TBD
16 MHz(6)
8.7
TBD
TBD
8 MHz
5.1
TBD
TBD
4 MHz
3.3
TBD
TBD
2 MHz
2.4
TBD
TBD
External clock(4), all
peripherals disabled
168 MHz
39.8
TBD
TBD
144 MHz
30.8
TBD
TBD
120 MHz
26
TBD
TBD
90 MHz
20.4
TBD
TBD
60 MHz
14.3
TBD
TBD
30 MHz
8.2
TBD
TBD
25 MHz
6.4
TBD
TBD
16 MHz(6)
4.75
TBD
TBD
8 MHz
3
TBD
TBD
4 MHz
2.3
TBD
TBD
2 MHz
2
TBD
TBD
1.
Code and data processing running from SRAM1 using boot pins.
2.
TBD stands for “to be defined”.
3.
Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
4.
External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
5.
When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
6.
In this case HCLK = system clock/2.


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