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STM32F405XX Datasheet(PDF) 79 Page - STMicroelectronics |
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STM32F405XX Datasheet(HTML) 79 Page - STMicroelectronics |
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79 / 154 page  STM32F405xx, STM32F407xx Electrical characteristics Doc ID 022152 Rev 1 79/154 Jitter(4) Cycle-to-cycle jitter System clock 120 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples -32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples -40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples -330 - Main clock output (MCO) for RMMI Ethernet Long term Jitter, PLL input=6.25MHz -1.6 - ns IDD(PLL) (5) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL) (5) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. Maximum input PLL frequency is recommended for applications sensitive of long term jitter. 4. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 5. Based on characterization, not tested in production. Table 31. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 32. PLLI2S (audio PLL) characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(2) 0.95(3) 12.0(4) MHz fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz fVCO_OUT PLLI2S VCO output 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 |
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