2.3GHz to 2.7GHz MIMO Wireless

BroadbandRF Transceiver

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9

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

4-WIRE SERIAL PARALLEL INTERFACE TIMING (see Figure 1)

SCLK Rising Edge to CS Falling

Edge Wait Time

6ns

Falling Edge of CS to Rising

Edge of First SCLK Time

6ns

DIN to SCLK Setup Time

6ns

DIN to SCLK Hold Time

6ns

SCLK Pulse-Width High

6ns

SCLK Pulse-Width Low

6ns

Last Rising Edge of SCLK to

Rising Edge of CS or Clock to

Load Enable Setup Time

6ns

CS High Pulse Width

20

ns

Time Between Rising Edge of CS

and the Next Rising Edge of

SCLK

6ns

Clock Frequency

40

MHz

Rise Time

ns

Fall Time

ns

SCLK Falling Edge to Valid DOUT

12.5

ns

AC ELECTRICAL CHARACTERISTICS—TIMING (continued)

design and characterization. The power-on default register settings are not production tested. Load register setting 10µs

Note 3: Tx mode supply current is specified for 64 QAM while achieving the Tx output spectrum mask shown in the

Typical Operating

Characteristics. The supply current can be reduced for 16 QAM signal by adjusting the Tx bias settings through the SPI.

Note 4: Two tones at +20MHz and +39MHz offset with -35dBm/tone. Measure IM3 at 1MHz.

Note 5: Gain adjusted over max gain and max gain -3dB.