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LPC1756FBD80 Datasheet(PDF) 2 Page - NXP Semiconductors |
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LPC1756FBD80 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 74 page LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 29 March 2011 2 of 74 NXP Semiconductors LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces: On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller. USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only. Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support. CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels. SPI controller with synchronous, serial, full duplex communication and programmable data length. Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode. On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. Other peripherals: 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. One motor control PWM with support for three-phase motor control. Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. ARM Cortex-M3 system tick timer, including an external clock input option. |
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