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UCC28950 Datasheet(PDF) 38 Page - Texas Instruments |
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UCC28950 Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 46 page  1 kW + R Z1 C Z1 C P1 EA- EA+ R I R V REF R R D C Z2 R Z2 V OUT When evaluating COMP, for best results put a 1-kW resistor between COMP and probe. UCC28950 SLUSA16A – MARCH 2010 – REVISED JULY 2010 www.ti.com It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output inductor at the light load, during parallel operation and at some transient conditions. Such reverse current results in circulating of some extra energy between the input voltage source and the load and, therefore, causes increased losses and reduces efficiency. Another negative effect of such reverse current is the loss of ZVS condition. The suggested control algorithm prevents reverse current flow, still maintaining most of the benefits of synchronous rectification by switching off the drive signals of rectifier MOSFETs in a predetermined way. At some pre-determined load current threshold, the controller disables outputs OUTE and OUTF by bringing them down to zero. Synchronous rectification using MOSFETs requires some electrical energy to drive the MOSFETs. There is a condition below some light-load threshold when the MOSFET drive related losses exceed the saving provided by the synchronous rectification. At such light load, it is best to disable the drive circuit and use the internal body diodes of rectifier MOSFETs, or external diodes in parallel with the MOSFETs, for more efficient rectification. In most practical cases, the drive circuit needs to be disabled close to DCM mode. This mode of operation is called discontinuous-current diode-rectification mode. At very light-load and no-load condition, the duty cycle, demanded by the closed-feedback-loop control circuit for output voltage regulation, can be very low. This could lead to the loss of ZVS condition and increased switching losses. To avoid the loss of ZVS, the control circuit limits the minimum ON-time pulse applied to the power transformer using resistor from TMIN pin to GND. Therefore, the only way to maintain regulation at very light load and at no-load condition is to skip some pulses. The controller skips pulses in a controllable manner to avoid saturation of the power transformer. Such operation is called burst mode. In Burst Mode there are always an even number of pulses applied to the power transformer before the skipping off time. Thus, the flux in the core of the power transformer always starts from the same point during the start of every burst of pulses. Voltage Loop Compensation Recommendation For best results in the voltage loop it is recommended to use Type 2 or Type 3 compensation network (Figure 49). A type 2 compensation network does not require passive components CZ2 and RZ2. Type 1 compensation is not versatile enough for a phase shifted full bridge. When evaluating the COMP for best results it is recommended to put a 1-k Ω resistor between the scope probe and the COMP pin of the UCC28950. Figure 49. Type 3 Compensation Evaluation 38 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC28950 |
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