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SN65C1168N Datasheet(PDF) 7 Page - Texas Instruments |
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SN65C1168N Datasheet(HTML) 7 Page - Texas Instruments |
7 / 20 page SN65C1167 SN75C1167, SN65C1168, SN75C1168 www.ti.com SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009 RECEIVER SECTION Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Positive-going input threshold voltage, differential VIT+ 0.2 V input Negative-going input threshold voltage, differential VIT– −0.2(2) V input Vhys Input hysteresis (VIT+ – VIT–) 60 mV VIK Input clamp voltage, RE SN75C1167 II = −18 mA −1.5 V VOH High-level output voltage VID = 200 mV, IOH = −6 mA 3.8 4.2 V VOL Low-level output voltage VID = −200 mV, IOL = 6 mA 0.1 0.3 V High-impedance-state output IOZ SN75C1167 VO = VCC or GND ±0.5 ±5 µA current VI = 10 V 1.5 II Line input current Other input at 0 V mA VI = −10 V −2.5 II Enable input current, RE SN75C1167 VI = VCC or GND ±1 µA ri Input resistance VIC = −7 V to 7 V, Other input at 0 V 4 17 k Ω VI = VCC or GND 4 6 ICC Supply current (total package) No load, Enabled mA VIH = 2.4 V or 0.5 V (3) 5 9 (1) All typical values are at VCC = 5 V and TA = 25°C. (2) The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. (3) Refer to TIA/EIA-422-B for exact conditions. Switching Characteristics over operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT tPLH Propagation delay time, low- to high-level output 9 17 27 ns See Figure 5 tPHL Propagation delay time, high- to low-level output 9 17 27 ns tTLH Transition time, low- to high-level output 4 9 ns VIC = 0 V, See Figure 5 tTHL Transition time, high- to low-level output 4 9 ns tPZH Output enable time to high level 13 22 ns tPZL Output enable time to low level 13 22 ns RL = 1 kW, See Figure 6 tPHZ Output disable time from high level 13 22 ns tPLZ Output disable time from low level 13 22 ns (1) Measured per input while the other inputs are at VCC or GND (2) All typical values are at VCC = 5 V and TA = 25°C. Copyright © 1993–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SN65C1167 SN75C1167 SN65C1168 SN75C1168 |
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