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RM48L550ZWTT Datasheet(PDF) 1 Page - Texas Instruments |
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RM48L550ZWTT Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 157 page  RM48L950 RM48L750 RM48L550 www.ti.com SPNS174 – SEPTEMBER 2011 RM48Lx50 16/32-Bit RISC Flash Microcontroller Check for Samples: RM48L950 1 RM48Lx50 16/32-Bit RISC Flash Microcontroller 1.1 Features 1 • High-Performance Microcontroller for Safety • Multiple Communication Interfaces Critical Applications – 10/100 Mbps Ethernet MAC (EMAC) – Dual CPU’s running in lockstep • IEEE 802.3 compliant (3.3V-I/O only) – ECC on flash and RAM interfaces • Supports MII and MDIO – Built-In Self Test for CPU and on-chip RAMs – USB – Error Signaling Module with Error Pin • 2-port USB Specification, revision – Voltage and Clock Monitoring 2.0-compatible host controller, based on the OHCI Specification for USB, release • ARM® Cortex™ – R4F 32-bit RISC CPU 1.0 – Efficient 1.6DMIPS/MHz with 8-stage pipeline • One full-speed USB device compatible – Floating-Point Unit with Single/Double with the USB Specification, revision 2.0 Precision and USB Specification, revision 1.1 – 12-Region Memory Protection Unit – Three CAN Controllers (DCAN) – Open Architecture with 3rd Party Support • 64 mailboxes with parity protection each • Operating Conditions • Compliant to CAN protocol version 2.0B – Up to 200MHz System Clock – Inter-Integrated Circuit (I2C) – Core Supply Voltage (VCC): 1.2V nominal – Three Multi-buffered Serial Peripheral – I/O Supply Voltage (VCCIO): 3.3V nominal Interfaces (MibSPI) • Integrated Memory • 128 Words with Parity Protection each – Up to 3MB Program Flash with ECC – Two Standard Serial Peripheral Interfaces – Up to 256KB RAM with ECC (SPI) – 64KB Flash for emulated EEPROM – Local Interconnect Network Interface (LIN) • 16- bit External Memory Interface Controller • Common Platform Architecture • Compliant to LIN protocol version 2.1 – Consistent memory map across family – Standard Serial Communication Interface – Real-Time Interrupt Timer (RTI) OS Timer (SCI) – 96-channel Vectored Interrupt Module (VIM) • Two High-End Timer Modules (N2HET) – 2-channel Cyclic Redundancy Checker (CRC) – N2HET1: 32 programmable channels • Direct Memory Access (DMA) Controller – N2HET2: 20 programmable channels – 16 Channels and 32 Control Packets – 160 Word Instruction RAM with parity protection each – Parity protection for control packet RAM – Each includes Hardware Angle Generator – DMA Accesses Protected by Dedicated MPU – Dedicated Transfer Unit for each N2HET • Frequency-Modulated Phase-Locked-Loop (HTU) (FMPLL) with Built-In Slip Detector • Two 10/12-bit Multi-Buffered ADC Modules • Separate Non-Modulating PLL – ADC1: 24 channels • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components – ADC2: 16 channels • JTAG Security Module – 16 shared channels • Trace and Calibration Capabilities – 64 result buffers with parity protection each – Embedded Trace Macrocell (ETM-R4) • Packages – Data Modification Module (DMM) – 144-pin Quad Flatpack (PGE) [Green] – RAM Trace Port (RTP) – 337-Ball Grid Array (ZWT) [Green] – Parameter Overlay Module (POM) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative Copyright © 2011, Texas Instruments Incorporated or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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