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ISL85033 Datasheet(PDF) 22 Page - Intersil Corporation |
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ISL85033 Datasheet(HTML) 22 Page - Intersil Corporation |
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22 / 26 page  ISL85033 22 FN6676.4 September 22, 2011 exponentially increasing with temperature. Due to the nature of reverse bias leakage vs temperature, the diode should be carefully selected to operate in the worst case circuit conditions. Catastrophic failure is possible if the diode chosen experiences thermal runaway at elevated temperatures. Please refer to Application Note for diode selection. Power Derating Characteristics To prevent the ISL85033 from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by Equation 28: where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by Equation 29: where TA is the ambient temperature. For the QFN package, the θJA is +38°C/W. The actual junction temperature should not exceed the absolute maximum junction temperature of +125°C When considering the thermal design, remember to consider the thermal needs of the rectifier diode. The ISL85033 delivers full current at ambient temperatures up to +85°C if the thermal impedance from the thermal pad maintains the junction temperature below the thermal shutdown level, depending on the Input Voltage/Output Voltage combination and the switching frequency. The device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 49 illustrates the power derating versus ambient temperature for the ISL85033 EVAL kit. Note that the EVAL kit derating curve is based on total circuit dissipation, not IC dissipation alone. Layout Considerations Layout is very important in high frequency switching converter design. With power devices switching efficiently between 100kHz and 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes these voltage spikes. As an example, consider the turn-off transition of the upper MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the Schottky diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL85033 switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next, are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 50 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. In order to dissipate heat generated by the internal LDO and MOSFET, the ground pad should be connected to the internal ground plane through at least four vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL85033 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper and Schottky diode and the load. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required. TRISE PD () θJA () = (EQ. 28) TJ TA TRISE + () = (EQ. 29) 0 10 20 30 40 50 60 70 80 90 100 110 120 0 123 4 5 67 89 10 11 12 ISL85033EVAL1ZB EVAL BOARD TOTAL POWER DISSIPATION (W) ΘJA = 38°C/W FIGURE 49. POWER DERATING CURVE |
Similar Part No. - ISL85033_11 |
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Similar Description - ISL85033_11 |
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