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RFSA2624

DS110408

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Truth Table

Note: C 0.5=D0, C1=D1, ... C16=D5 (for the purpose of the example below)

Serial Port Interface

Control Bit

Relative Gain

Setting

C16

C8

C4C2C1

C0.5

1111

11

Max gain

1111

10

-0.5dB

1111

01

-1dB

1110

11

-2dB

1101

11

-4dB

1011

11

-8dB

0111

11

-16dB

0000

00

-31.5dB

SPI Timing Diagram Specifications

Parameter

Limit

Unit

Comment

LOGIC Voltage Levels

t1

25

MHz max

CLK Frequency

State

Logic

t2

20

ns min

CLK High

Low

0V to 0.8V

t3

20

ns min

CLK Low

High

2.0V to 5.0V

t4

5

ns min

DATA to CLK Setup Time

t5

5

ns min

DATA to CLK Hold Time

t6

30

ns min

Data Valid

t7

5

ns min

LE to CLK Setup Time

t8

5

ns min

CLK to LE Setup Time

t9

10

ns min

LE Pulse Width

t10

20

ns min

Output Set

CLK

DATA

t6

LE

t1

t2

t3

t4

t5

t7

t8

DOUT

t9

SPI Timing Diagram

t10

Programming example – 6-bit

MSB

LSB

D4

D3

D2

D0

D1

D5

CLK

DATA

LE