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LH540225 Datasheet(PDF) 1 Page - Sharp Corporation |
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LH540225 Datasheet(HTML) 1 Page - Sharp Corporation |
1 / 48 page LH540215/25 512 × 18 / 1024 × 18 Synchronous FIFO FEATURES •• Fast Cycle Times: 20/25/35 ns •• Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs •• Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal •• Device Comes Up into One of Two Known Default States at Reset Depending on the State of the EMODE Control Input: Programming is Allowed, but is not Required •• Internal Memory Array Architecture Based on CMOS Dual-Port SRAM Technology, 512 × 18 or 1024 × 18 •• ‘Synchronous’ Enable-Plus-Clock Control at Both Input Port and Output Port •• Independently-Synchronized Operation of Input Port and Output Port •• Control Inputs Sampled on Rising Clock Edge •• Most Control Signals Assertive-LOW for Noise Immunity •• May be Cascaded for Increased Depth, or Paralleled for Increased Width •• Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are Programmable •• In Enhanced Operating Mode, Almost-Full, Half-Full, and Almost-Empty Flags can be Made Completely Synchronous •• In Enhanced Operating Mode, Duplicate Enables for Interlocked Paralleled FIFO Operation, for 36-Bit Data Width, when Selected and Appropriately Connected •• In Enhanced Operating Mode, Disabling Three-State Outputs May be Made to Suppress Reading •• Data Retransmit Function •• TTL/CMOS-Compatible I/O •• Space-Saving 68-Pin PLCC Package, and 64-Pin TQFP Package RESET LOGIC INPUT PORT RS INPUT PORT CONTROL LOGIC READ POINTER WRITE POINTER DEDICATED AND PROGRAMMABLE STATUS FLAGS FIFO MEMORY ARRAY 512 x 18/1024 x 18 OUTPUT PORT CONTROL LOGIC FF PAF WXO/HF RXO /EF2 PAE D0 - D17 WEN WCK Q0 - Q17 RCK OUTPUT PORT REN OE PROGRAMMABLE REGISTERS EXPANSION LOGIC WXI/ WEN2 FL/ RT WXO/HF RXI/ REN2 RXO/ EF2 LD 540215-1 WXI/ WEN2 RXI/ REN2 BOLD ITALIC = Enhanced Operating Mode. EMODE EF Figure 1. LH540215/25 Block Diagram BOLD ITALIC = Enhanced Operating Mode 1 |
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