Electronic Components Datasheet Search
  English  ▼


LH540215 Datasheet(PDF) 15 Page - Sharp Corporation

Part # LH540215
Description  512 x 18 / 1024 x 18 Synchronous FIFO
Download  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SHARP [Sharp Corporation]
Direct Link  http://sharp-world.com/
Logo SHARP - Sharp Corporation

LH540215 Datasheet(HTML) 15 Page - Sharp Corporation

Back Button LH540215 Datasheet HTML 11Page - Sharp Corporation LH540215 Datasheet HTML 12Page - Sharp Corporation LH540215 Datasheet HTML 13Page - Sharp Corporation LH540215 Datasheet HTML 14Page - Sharp Corporation LH540215 Datasheet HTML 15Page - Sharp Corporation LH540215 Datasheet HTML 16Page - Sharp Corporation LH540215 Datasheet HTML 17Page - Sharp Corporation LH540215 Datasheet HTML 18Page - Sharp Corporation LH540215 Datasheet HTML 19Page - Sharp Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 48 page
background image
Data Inputs
DATA IN (D0 – D17)
Data, programmable-flag-offset values, and
Register codes are input to the FIFO as 18-bit words on
D0 – D17. Unused bit positions in offset-value and Con-
trol-Register words should be zero-filled.
Control Inputs
The FIFO is reset whenever the asynchronous Reset
(RS) input is taken to a LOW state. A reset operation is
required after power-up, before the first write operation
may occur. The state of the FIFO is fully defined after a
reset operation. If the default values which are entered
into the Programmable-Flag-Offset-Value Registers
the Control Register by a reset operation are accept-
able, then no device programming is required. A reset
operation initializes the FIFO’s internal read-address and
write-address pointers to the FIFO’s first physical memory
location. The five status flags, FF, PAF, HF, PAE, and EF,
are updated to indicate that the FIFO is completely empty;
thus, the first three of these are reset to HIGH, and the
last two are reset to LOW. The flag-offset values for PAF
and PAE each are initialized to one-eighth of the depth of
a single FIFO, minus one; 63 for a 512-word FIFO, and
127 for a 1024-word FIFO. If
EMODE is not being as-
serted (i.e., if
EMODE is HIGH), all Control Register bits
are initialized to LOW, to configure the FIFO to operate in
the IDT72215B/25B-Compatible Operating Mode. Until a
write operation occurs, the data outputs D0 – D17 all are
LOW whenever OE is LOW.
Whenever EMODE is asserted during a reset op-
eration, Control Register bits 00 – 05 remain HIGH
rather than LOW after the completion of the reset
operation. Thus, EMODE has the effect of activating
all of the Enhanced-Operating-Mode features during
a reset operation. Subsequently, they may be indi-
vidually disabled or re-enabled by changing the set-
ting of Control-Register bits. The behavior of these
Enhanced-Operating-Mode features is described in
Table 5. For permanent Enhanced-Operating-Mode
operation, EMODE must be grounded; dynamic con-
trol of EMODE during system operation is not recom-
Asserting EMODE during a reset operation also
causes WXI/WEN2 to be configured as WEN2, and
RXI/REN2 to be configured as REN2, to support inter-
locked-paralleled operation of two FIFOs ‘side by
side. (See Figure 27.) Additionally, RXO/EF2 is config-
ured as EF2, which duplicates the EF signal with one
extra RCK cycle delay, in order to provide proper
timing for ‘pipelined’ cascaded operation.
A rising edge (LOW-to-HIGH transition) of WCLK initi-
ates a FIFO write cycle if LD is HIGH, or a programma-
ble-register write cycle if LD is LOW. The 18 data inputs,
and all input-side synchronous control inputs, must meet
setup and hold times with respect to the rising edge of
WCLK. The input-side status flags are meaningful after
specified time intervals, following a rising edge of WCLK.
Conceptually, the WCLK input receives a free-running,
periodic ‘clock’ waveform, which is used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that the WCLK waveform
must be periodic. An ‘asynchronous’ mode of operation
is in fact possible, if WEN is continuously asserted (that
is, is continuously held LOW), and WCLK receives ape-
riodic ‘clock’ pulses of suitable duration. There likewise is
no requirement that WCLK must have any particular
synchronization relation to the read clock RCLK. These
two clock inputs may in fact receive the same ‘clock’
signal; or they may receive totally-different signals, which
are not synchronized to each other in any way.
Whenever WEN is being asserted (is LOW) and LD is
HIGH, and the FIFO is not full, an 18-bit data word is
loaded into the effective input register for the memory
array at every WCLK rising edge (LOW-to-HIGH transi-
tion). Data words are stored into the two-port memory
array sequentially, regardless of any ongoing read opera-
tion. Whenever WEN is not being asserted (is HIGH), the
input register retains whatever data word it contained
previously, and no new data word gets loaded into the
memory array.
To prevent overrunning the internal FIFO boundaries,
further write operations are inhibited whenever the Full
Flag (FF) is being asserted (is LOW). If a valid read
operation then occurs, upon the completion of that read
cycle FF again goes HIGH after a time tWFF, and another
write operation is allowed to begin whenever WCLK
makes another LOW-to-HIGH transition. Effectively,
WEN is overridden by FF; thus, during normal FIFO
operation, WEN has no effect when the FIFO is full.
In the Enhanced Operating Mode, whenever
EMODE is being asserted (is LOW), WXI/WEN2 func-
tions as WEN2, an additional duplicate (albeit asser-
tive-HIGH) write-enable input, in order to provide
an‘interlocking’ mechanism for reliable synchro-
nization of two paralleled FIFOs. To control writing,
WEN2 is ANDed with WEN; this logic-AND function
• WEN2) then behaves like WEN in the forego-
ing description.
BOLD ITALIC = Enhanced Operating Mode
512 x 18/1024 x 18 Synchronous FIFO

Similar Part No. - LH540215

ManufacturerPart #DatasheetDescription
Sharp Corporation
LH540202 SHARP-LH540202 Datasheet
156Kb / 18P
   CMOS 1024 x 9 Asynchronous FIFO
LH540203 SHARP-LH540203 Datasheet
156Kb / 17P
   CMOS 2048 x 9 Asynchronous FIFO
LH540203D SHARP-LH540203D Datasheet
156Kb / 17P
LH540203D-15 SHARP-LH540203D-15 Datasheet
156Kb / 17P
LH540203D-20 SHARP-LH540203D-20 Datasheet
156Kb / 17P
More results

Similar Description - LH540215

ManufacturerPart #DatasheetDescription
Integrated Device Techn...
IDT72511 IDT-IDT72511 Datasheet
434Kb / 28P
   PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
IDT72510 IDT-IDT72510 Datasheet
440Kb / 32P
   BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT
IDT72205LB IDT-IDT72205LB Datasheet
181Kb / 16P
   CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
Sharp Corporation
LH543611 SHARP-LH543611 Datasheet
475Kb / 57P
   512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
Texas Instruments
SN74V215 TI-SN74V215_06 Datasheet
590Kb / 43P
[Old version datasheet]   512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V215 TI-SN74V215_08 Datasheet
600Kb / 43P
[Old version datasheet]   512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V215 TI-SN74V215 Datasheet
555Kb / 40P
[Old version datasheet]   512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
Sharp Corporation
LH543620 SHARP-LH543620 Datasheet
269Kb / 38P
   1024 x 36 Synchronous FIFO
Integrated Device Techn...
IDT72V205 IDT-IDT72V205 Datasheet
214Kb / 25P
   3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
Cypress Semiconductor
CY7C4205 CYPRESS-CY7C4205_11 Datasheet
689Kb / 25P
   256/512/1K/4K x 18 Synchronous FIFOs
More results

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Go To PDF Page

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com