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LH540203 Datasheet(PDF) 2 Page - Sharp Corporation

Part # LH540203
Description  CMOS 2048 x 9 Asynchronous FIFO
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Manufacturer  SHARP [Sharp Corporation]
Direct Link  http://sharp-world.com/
Logo SHARP - Sharp Corporation

LH540203 Datasheet(HTML) 2 Page - Sharp Corporation

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Data words are read out from the LH540203’s output
port in precisely the same order that they were written in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device’s memory is internally predefined, no
external addressing information is required for the opera-
tion of the LH540203 device.
Drop-in-replacement compatibility is maintained with
both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.
The Retransmit (RT) control signal causes the internal
FIFO-memory-array read-address pointer to be set back
to zero, to point to the LH540203’s first physical memory
location, without affecting the internal FIFO-memory-
array write-address pointer. Thus, the Retransmit control
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-address-pointer value, may be read out
repeatedly
an arbitrary number of times. The only restrictions are that
neither the read-address pointer nor the write-address
pointer may ‘wrap around’ during this entire process, i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540203 is operating in a depth-expanded
configuration.
The Reset (RS) control signal returns the LH540203
to an initial state, empty and ready to be filled. An
LH540203 should be reset during every system power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540203’s first physical memory location. Any informa-
tion which previously had been stored within the
LH540203 is not recoverable after a reset operation.
Acascading (depth-expansion) scheme may be imple-
mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This allows a
deeper ‘effective FIFO’ to be implemented by using two
or more LH540203 devices, without incurring additional
latency (‘fallthrough’ or ‘bubblethrough’) delays, and with-
out the necessity of storing and retrieving any given data
word more than once. In this cascaded operating mode,
one LH540203 device must be designated as the ‘first-
load’ or ‘master’ device, by grounding its First-Load
(FL/RT) control input; the remaining LH540203 devices
are designated as ‘slaves,’ by tying their FL/RT inputs
HIGH. Because of the need to share control signals on
pins, the Half-Full Flag and the retransmission capability
are not available for either ‘master’ or ‘slave’ LH540203
devices operating in cascaded mode.
FUNCTIONAL DESCRIPTION (cont’d)
DATA OUTPUTS
Q0 - Q8
FLAG
LOGIC
WRITE
POINTER
READ
POINTER
DATA INPUTS
D0 - D8
DUAL-PORT
RAM
ARRAY
2048 x 9
EF
FF
. . .
540203-1
INPUT
PORT
CONTROL
R
W
RESET
LOGIC
RS
OUTPUT
PORT
CONTROL
EXPANSION
LOGIC
XO/HF
XI
FL/RT
Figure 3.
LH540203 Block Diagram
LH540203
CMOS 2048
× 9 Asynchronous FIFO
2


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