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LH5324500 Datasheet(PDF) 1 Page - Sharp Corporation |
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LH5324500 Datasheet(HTML) 1 Page - Sharp Corporation |
1 / 7 page LH5324500 FEATURES •• 3,145,728 words × 8 bit organization (Byte mode) 1,572,864 words × 16 bit organization (Word mode) •• Access time: 150 ns (MAX.) •• Power consumption: Operating: 357.5 mW (MAX.) Standby: 550 µW (MAX.) •• Static operation •• TTL compatible I/O •• Three-state outputs •• Single +5 V power supply •• Package: 44-pin, 600-mil SOP DESCRIPTION The LH5324500 is a 24M-bit mask-programmable ROM organized as 3,145,728 × 8 bits (Byte mode) or 1,572,864 × 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 5324500-1 TOP VIEW 2 3 4 5 8 9 A2 A5 39 38 37 36 35 34 31 28 A7 A6 6 7 A3 A4 33 32 A10 A11 A13 A15 BYTE GND D14 10 11 12 41 40 A9 A1 13 30 D15/A-1 (LSB) 29 D7 OE A0 CE A12 44-PIN SOP 14 15 16 17 18 19 20 21 25 27 26 24 23 D13 D5 D12 D4 D2 D10 D9 GND D8 D1 D0 D3 D11 VCC A8 A14 A16 D6 42 1 A18 NC 22 44 43 A17 A19 A20 Figure 1. Pin Connections for SOP Package CMOS 24M (3M × 8/1.5M × 16) MROM 1 |
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