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LH28F008SA-85 Datasheet(PDF) 10 Page - Sharp Corporation |
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LH28F008SA-85 Datasheet(HTML) 10 Page - Sharp Corporation |
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10 / 27 page  LH28F008SA 8M (1M × 8) Flash Memory 10 Read Array Command Upon initial device powerup and after exit from deep powerdown mode, the LH28F008SA defaults to Read Array mode. This operation is also initiated by writing FFH into the Command User Interface. Microprocessor read cycles retrieve array data. The device remains en- abled for reads until the Command User Interface con- tents are altered. Once the internalWrite State Machine has started a block erase or byte write operation, the device will not recognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional when VPP = VPPL or VPPH. Intelligent Identifier Command The LH28F008SA contains an intelligent identifier operation, initiated by writing 90H into the Command User Interface. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H. To terminate the opera- tion, it is necessary to write another valid command into the register. Like the Read Array command, the intelli- gent identifier command is functional when VPP = VPPL or VPPH. Read Status Register Command The LH28F008SA contains a Status Register which may be read to determine when a byte write or block erase operation is complete, and whether that opera- tion completed successfully. The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command User Interface. After writing this command, all subsequent read operations output data from the Status Register, until another valid command is written to the Command User Interface. The contents of the Status Register are latched on the falling edge of OE » or CE », whichever occurs last in the read cycle. OE » or CE » must to toggled to VIH before further reads to update the Status Register latch. The Read Status Register command functions when VPP = VPPL or VPPH. Clear Status Register Command The Erase Status and Byte Write Status bits are set to '1's by theWrite State Machine and can only be reset by the Clear Status Register Command. These bits indicate various failure conditions (see Status Register Definitions). By allowing system software to control the resetting of these bits, several operations may be per- formed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). The Status Reg- ister may then be polled to determine if an error occurred during that sequence. This adds flexibility to the way the device may be used. Additionally, the VPP Status bit (SR.3) MUST be re- set by system software before further byte writes or block erases are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the Command User Interface. The Clear Status Register command is functional when VPP = VPPL or VPPH. Erase Setup/Erase Confirm Commands Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup com- mand (20H) is first written to the Command User Inter- face, followed by the Erase Confirm command (D0H). These commands require both appropriate sequenc- ing and an address within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After the two-command erase sequence is writ- ten to it, the LH28F008SA automatically outputs Status Register data when read (see Block Erase Flowchart). The CPU can detect the completion of the erase event by analyzing the output of the RY »/BY » pin, or the WSM Status bit of the Status Register. When erase is completed, the Erase Status bit should be checked. If erase error is detected, the Status Reg- ister should be cleared. The Command User Interface remains in Read Status Register mode until further com- mands are issued to it. This two-step sequence of set-up followed by execution insures that memory contents are not accidentially erased. Also, reliable block erasure can only occur when VPP = VPPH. In the absence of this high voltage, memory contents are protected against era- sure. If block erase is attempted while VPP = VPPL, the VPP Status bit will be set to '1'. Erase attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. Erase Suspend/Erase Resume Commands The Erase Suspend command allows block erase interruption in order to read data from another block of memory. Once the erase process starts, writing the Erase Suspend command (B0H) to the Command User Interface requests that the WSM suspend the erase sequence at a predetermined point in the erase algo- rithm. The LH28F008SA continues to output Status Register data when read, after the Erase Suspend com- mand is written to it. Polling the WSM Status and Erase Suspend Status bits will determined when the erase operation has been suspended (both will be set to '1'). RY »/BY » will also transition to VOH. |
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Similar Description - LH28F008SA-85 |
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