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LTC2635-LZ8 Datasheet(PDF) 10 Page - Linear Technology |
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LTC2635-LZ8 Datasheet(HTML) 10 Page - Linear Technology |
10 / 32 page LTC2635 0 2635fb electrical characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance tS Settling Time VCC = 5V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.9 4.3 5 µs µs µs Voltage Output Slew Rate 1 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 3 nV • s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switched 0 to FS 3 nV • s Multiplying Bandwidth External Reference 320 kHz en Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 250 230 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1µF 35 50 680 750 µVP-P µVP-P µVP-P µVP-P timing characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13) LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCL SCL Clock Frequency l 0 400 kHz tHD(STA) Hold Time (Repeated) Start Condition l 0.6 µs tLOW Low Period of the SCL Clock Pin l 1.3 µs tHIGH High Period of the SCL Clock Pin l 0.6 µs tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 µs tHD(DAT) Data Hold Time l 0 0.9 µs tSU(DAT) Data Set-Up Time l 100 ns tr Rise Time of Both SDA and SCL Signals (Note 12) l 20+0.1CB 300 ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20+0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 µs tBUF Bus Free Time Between a Stop and Start Condition l 1.3 µs t1 Falling Edge of 9th Clock of the 3rd Input Byte to LDAC High or Low Transition l 400 ns t2 LDAC Low Pulse Width l 20 ns |
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