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BD4154FV Datasheet(PDF) 13 Page - Rohm

Part No. BD4154FV
Description  Power Switch IC for ExpressCard
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Maker  ROHM [Rohm]
Homepage  http://www.rohm.com
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BD4154FV Datasheet(HTML) 13 Page - Rohm

 
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BD4154FV
Technical Note
13/15
www.rohm.com
2010.04 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
Notes for Use
1.Absolute maximum ratings
Although quality is rigorously controlled, the device may be destroyed when applied voltage, operating temperature, etc.
exceeds its absolute maximum rating. Because the source (short mode or open mode) cannot be identified once the IC
is destroyed, it is important to take physical safety measures such as fusing when implementing any special mode that
operates in excess of absolute rating limits.
2.Thermal design
Consider allowable loss (Pd) under actual operating conditions and provide sufficient margin in the thermal design.
3.Terminal-to-terminal short-circuit and mis-mounting
When the mounting the IC to a printed circuit board, take utmost care to assure the position and orientation of the IC are correct.
In the event that the IC is mounted erroneously, it may be destroyed. The IC may also be destroyed when a short-circuit is
caused by foreign matter introduced into the clearance between outputs, or between an output and power-GND.
4.Operation in strong electromagnetic fields
Using the IC in strong electromagnetic fields may cause malfunctions. Exercise caution in respect to electromagnetic fields.
5.Built-in thermal shutdown protection circuit
This IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C (standard value)
with a -15°C (standard value) hysteresis width. When the IC chip temperature rises the TSD circuit is activated, while the
output terminal is brought to the OFF state. The built-in TSD circuit is intended exclusively to shut down the IC in a thermal
runaway event, and is not intended to protect the IC or guarantee performance in these conditions. Therefore, do not
operate the IC after with the expectation of continued use or subsequent operation once this circuit is activated.
6.Capacitor across output and GND
When a large capacitor is connected across the output and GND, and the V3AUX_IN is short-circuited with 0V or GND for
any reason, current charged in the capacitor flows into the output and may destroy the IC. Therefore, use a capacitor
smaller than 1000 μF between the output and GND.
7.Set substrate inspection
Connecting a low-impedance capacitor to a pin when running an inspection with a set substrate may produce stress on the IC.
Therefore, be certain to discharge electricity at each process of the operation. To prevent electrostatic accumulation and
discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage, and
continue observing ESD-prevention procedures in all handling, transfer and storage operations. Before attempting to
connect the set substrate to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply
is OFF before removing the substrate from the test setup.
8.IC terminal input
This integrated circuit is a monolithic IC, with P substrate and P
+ isolation between elements.
The P layer and N layer of each element form a, PN junction. When the potential relation is GND>terminal A>terminal B,
the PN junction works as a diode, and when terminal B>GND terminal A, the PN junction operates as a parasitic transistor.
Parasitic elements inevitably form, due to the nature of the IC construction. The operation of the parasitic element gives
rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently, take
utmost care not to use the IC in a way that would cause the parasitic element to actively operate, such as applying voltage
lower than GND (P substrate) to the input terminal.
9. GND wiring pattern
If both a small signal GND and a high current GND are present, it is recommended that the patterns for the high current
GND and the small signal GND be separated. Proper grounding to the reference point of the set should also be provided.
In this way, the small signal GND voltage will by unaffected by the change in voltage stemming from the pattern wiring
resistance and the high current. Also, pay special attention to avoid undesirable wiring pattern fluctuations in any
externally connected GND component.
PIN A)
P+
P+
N
N
N
P
P substrate
GND
GND
N
P
N
C
B
E
GND
P+
P+
N
N
Resistor
NPN Transistor Structure (NPN)
PIN B)
Parasitic diode
GND
PIN A)
C
E
B
GND
Nearby other device
PIN B)
Parasitic diode
Parasitic diode
Parasitic diode
P substrate


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