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DS31408GN Datasheet(PDF) 2 Page - Maxim Integrated Products |
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DS31408GN Datasheet(HTML) 2 Page - Maxim Integrated Products |
2 / 6 page DS31408 2 Application Examples Typical Timing Card Application Example DS31408 to BITS/SSU TCXO or OCXO Monitor, Divider, Selector DPLL1 APLL and divider BITS Tx DPLL2 BITS Rx processor Timing Card (1 of 2) Backplane DS1, E1 or 2048 kHz from BITS/SSU Timing Card (2 of 2) Identical to Timing Card 1 Line Card (1 of N) Line Card (N of N) <N> <N> <N> <N> <1> <1> <1> <1> N N N N typically 19.44MHz, 25MHz or 8kHz, point-to-point or multidrop buses create derived DS1 or E1/2048kHz clock locked to selected clock activity and frequency monitoring, select highest priority valid input for each DPLL clock/data recovery, equalizer, framer, extract SSMs Stratum 2, 3E or 3: jitter/wander filtering, hitless switching, phase adjust, holdover selects best system clock, best recovered line clock. hitless switching, frequency conversion, jitter cleanup <0> <0> APLL, divider and fanout Line Card Timing IC (see Fig 2-2) to port SERDES from port SERDES ABRIDGED DATA SHEET |
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