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HMCAD1050-40 Datasheet(PDF) 11 Page - Hittite Microwave Corporation

Part No. HMCAD1050-40
Description  Dual 13/12-Bit 20/40 MSPS A/D Converter
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Maker  HITTITE [Hittite Microwave Corporation]
Homepage  http://www.hittite.com
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HMCAD1050-40 Datasheet(HTML) 11 Page - Hittite Microwave Corporation

 
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMCAD1050-40
v01.0411
Dual 13/12-Bit 20/40 MSPS
a/D Converter
always should be lower than the load on data outputs
to ensure sufficient timing margins.
the digital outputs can be set in tristate mode by set-
ting the oe_n signal high.
the HMCAD1050-40 employs digital offset correc-
tion. this means that the output code will be 4096 with
shorted inputs. However, small mismatches in para-
sitics at the input can cause this to alter slightly. the
offset correction also results in possible loss of codes
at the edges of the full scale range. With no offset
correction, the ADC would clip in one end before the
other, in practice resulting in code loss at the oppo-
site end. With the output being centered digitally, the
output will clip, and the out of range flags will be set,
before max code is reached. When out of range flags
are set, the code is forced to all ones for overrange
and all zeros for underrange.
note that the out of range flags (ornG) will behave
differently for 12 bit and 13 bit output. For 13 bit output
ornG will be set when digital output data are all ones
or all zeros. For 12-bit output the ornG flags will be
set when all twelve bits are zeros or ones and when
the thirteenth bit is equal to the rest of the bits.
Data Format Selection
the output data are presented on offset binary form
when DFrMt is low (connect to ovss). setting
DFrMt high (connect to ovDD) results in 2’s comple-
ment output format. Details are shown in table 3.
table 3: Data Format Description for 2vpp Full Scale range
Differential Input Voltage (IPx - INx)
Output Data: Dx_12 : Dx_0
(DFrMt = 0, offset Binary)
Output Data: Dx_12 : Dx_0
(DFrMt = 1, 2’s Complement)
1.0 v
1 1111 1111 1111
0 1111 1111 1111
+0.24mv
1 0000 0000 0000
0 0000 0000 0000
-0.24mv
0 1111 1111 1111
1 1111 1111 1111
-1.0v
0 0000 0000 0000
1 0000 0000 0000
the data outputs can be used in three different con-
figurations.
• Normal Mode:
All 13 bits are used. MsB is Dx_12 and LsB is Dx_0.
this mode gives optimum performance
• 12-bit Mode:
the LsB is left unconnected such that only 12 bits
are used. MsB is Dx_12 and LsB is Dx_1. this mode
gives slightly reduced performance due to increased
quantization noise.
• Reduced Full Scale Range Mode:
the full scale range is reduced from 2 vpp to 1 vpp
which is equivalent to 6 dB gain in the ADC frontend.
note that data are only available in 2’s complement
format in this mode. MsB is Dx_11 and LsB is Dx_0.
note that the codes will wrap around when exceeding
the full scale range, and that out of range bits should
be used to clamp output data. see section reference
voltages for details. this mode gives slightly reduced
performance
Reference Voltages
the reference voltages are internally generated and
buffered based on a bandgap voltage reference. no
external decoupling is necessary, and the reference
voltages are not available externally. this simplifies
usage of the ADC since two extremely sensitive pins,
otherwise needed, are removed from the interface.
If a lower full scale range is required the 13-bit output
word provides sufficient resolution to perform digital
scaling with an equivalent impact on noise compared
to adjusting the reference voltages.
A simple way to obtain 1.0vpp input range with a
12-bit output word is shown in table 4. note that only
2’s complement output data are available in this mode
and that out of range conditions must be determined
based on a two bit output. the output code will wrap
around when the code goes outside the full scale
range. the out of range bits should be used to clamp
the output data for overrange conditions.


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