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HMCAD1041-80 Datasheet(PDF) 11 Page - Hittite Microwave Corporation

Part No. HMCAD1041-80
Description  Single 10-Bit 65/80 MSPS A/D Converter
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Maker  HITTITE [Hittite Microwave Corporation]
Homepage  http://www.hittite.com
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HMCAD1041-80 Datasheet(HTML) 11 Page - Hittite Microwave Corporation

 
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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0 - 11
HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
If the clock is generated by other circuitry, it should
be re-timed with a low jitter master clock as the last
operation before it is applied to the ADC clock input.
Digital Outputs
Digital output data are presented on parallel CMos
form. the voltage on the ovDD pin set the levels of the
CMos outputs. the output drivers are dimensioned to
drive a wide range of loads for ovDD above 2.25v,
but it is recommended to minimize the load to ensure
as low transient switching currents and resulting noise
as possible. In applications with a large fanout or large
capacitive loads, it is recommended to add external
buffers located close to the ADC chip.
the timing is described in the timing Diagram section.
note that the load or equivalent delay on CK_eXt
always should be lower than the load on data outputs
to ensure sufficient timing margins.
the digital outputs can be set in tristate mode by set-
ting the oe_n signal high.
the HMCAD1041-80 employs digital offset correc-
tion. this means that the output code will be 4096 with
shorted inputs. However, small mismatches in para-
sitics at the input can cause this to alter slightly. the
offset correction also results in possible loss of codes
at the edges of the full scale range. With no offset
correction, the ADC would clip in one end before the
other, in practice resulting in code loss at the oppo-
site end. With the output being centered digitally, the
output will clip, and the out of range flags will be set,
before max code is reached. When out of range flags
are set, the code is forced to all ones for overrange
and all zeros for underrange.
Data Format Selection
the output data are presented on offset binary form
when DFrMt is low (connect to ovss). setting
DFrMt high (connect to ovDD) results in 2’s comple-
ment output format. Details are shown in table 3.
table 3: Data Format Description for 2vpp Full Scale range
Differential Input Voltage (IP - IN)
Output Data: D_9 : D_0
(DFrMt = 0, offset Binary
)
Output Data: D_9 : D_0
(DFrMt = 1, 2’s Complement)
1.0 v
11 1111 1111
01 1111 1111
+0.24mv
10 0000 0000
00 0000 0000
-0.24mv
01 1111 1111
11 1111 1111
-1.0v
00 0000 0000
10 0000 0000
Reference Voltages
the reference voltages are internally generated and
buffered based on a bandgap voltage reference. no
external decoupling is necessary, and the reference
voltages are not available externally. this simplifies
usage of the ADC since two extremely sensitive pins,
otherwise needed, are removed from the interface.
Operational Modes
the operational modes are controlled with the PD_n
and sLP_n pins. If PD_n is set low, all other control
pins are overridden and the chip is set in Power Down
mode. In this mode all circuitry is completely turned off
and the internal clock is disabled. Hence, only leak-
age current contributes to the Power Down Dissipa-
tion. the startup time from this mode is longer than
for sleep Mode as all references need to settle to their
final values before normal operation can resume.
the sLP_n signal can be used to set the full chip in
sleep Mode. In this mode internal clocking is disabled,
but some low bandwidth circuitry is kept on to allow for
a short startup time. However, sleep Mode represents
a significant reduction in supply current, and it can be
used to save power even for short idle periods.
the input clock should be kept running in all idle
modes. However, even lower power dissipation is pos-
sible in Power Down mode if the input clock is stopped.
In this case it is important to start the input clock prior
to enabling active mode.
Startup Initialization
the HMCAD1041-80 must be reset prior to normal
operation. this is required every time the power
supply voltage has been switched off. A reset is per-
formed by applying Power Down mode. Wait until a
stable supply voltage has been reached, and pull the
PD_n pin for the duration of at least one clock cycle.
the input clock must be running continuously during
this Power Down period and until active operation
is reached. Alternatively the PD pin can be kept low
during power-up, and then be set high when the power
supply voltage is stable.


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