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HMCAD1041-80 Datasheet(PDF) 10 Page - Hittite Microwave Corporation

Part No. HMCAD1041-80
Description  Single 10-Bit 65/80 MSPS A/D Converter
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Maker  HITTITE [Hittite Microwave Corporation]
Homepage  http://www.hittite.com
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HMCAD1041-80 Datasheet(HTML) 10 Page - Hittite Microwave Corporation

 
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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0 - 10
HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
Figure 6: transformer coupled input
Figure 7 shows AC-coupling using capacitors. resis-
tors from the CM_eXt output, rCM, should be used
to bias the differential input signals to the correct volt-
age. the series capacitor, CI, form the high-pass pole
with these resistors, and the values must therefore be
determined based on the requirement to the high-pass
cut-off frequency.
Figure 7: AC coupled input
note that startup time from sleep Mode and Power
Down Mode will be affected by this filter as the time
required to charge the series capacitors is dependent
on the filter cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of figure 8 can
be used. the configuration in figure 8 is designed to
attenuate the kickback from the ADC and to provide
an input impedance that looks as resistive as possible
for frequencies below nyquist. values of the series
inductor will however depend on board design and
conversion rate. In some instances a shunt capaci-
tor in parallel with the termination resistor (e.g. 33pF)
may improve ADC performance further. this capacitor
attenuate the ADC kick-back even more, and minimize
the kicks traveling towards the source. However, the
impedance match seen into the transformer becomes
worse.
Figure 8: Alternative input network
Clock Input and Jitter Considerations
typically high-speed ADCs use both clock edges to
generate internal timing signals. In the HMCAD1041-
80 only the rising edge of the clock is used. Hence,
input clock duty cycles between 20% and 80% are
acceptable.
the input clock can be supplied in a variety of formats.
the clock pins are AC-coupled internally. Hence a
wide common mode voltage range is accepted. Differ-
ential clock sources as LvDs, LvPeCL or differential
sine wave can be connected directly to the input pins.
For CMos inputs, the CKn pin should be connected
to ground, and the CMos clock signal should be con-
nected to CKP. For differential sine wave clock, the
input amplitude must be at least ± 800 mvpp.
the quality of the input clock is extremely important
for high-speed, high-resolution ADCs. the contribu-
tion to snr from clock jitter with a full scale signal at a
given frequency is shown in equation 1,
SNR
jitter = 20 · log (2 · π · ƒIN · єt)
(1)
where fIn is the signal frequency, and
εt is the total
rms jitter measured in seconds. the rms jitter is the
total of all jitter sources including the clock generation
circuitry, clock distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable
performance, it is of utmost importance to limit the
clock jitter. this can be obtained by using precise and
stable clock references (e.g. crystal oscillators with
good jitter specifications) and make sure the clock dis-
tribution is well controlled. It might be advantageous
to use analog power and ground planes to ensure
low noise on the supplies to all circuitry in the clock
distribution. It is of utmost importance to avoid cross-
talk between the ADC output bits and the clock and
between the analog input signal and the clock since
such crosstalk often results in harmonic distortion.
the jitter performance is improved with reduced rise
and fall times of the input clock. Hence, optimum jitter
performance is obtained with LvDs or LvPeCL clock
with fast edges. CMos and sine wave clock inputs will
result in slightly degraded jitter performance.


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