HMCAD1041-80 datasheet(5/12 Pages) HITTITE | Single 10-Bit 65/80 MSPS A/D Converter

Part #	HMCAD1041-80

Description	Single 10-Bit 65/80 MSPS A/D Converter

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Manufacturer	HITTITE [Hittite Microwave Corporation]

Direct Link	http://www.hittite.com

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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

Application Support: apps@hittite.com

0

0 - 5

HMCAD1041-80

v01.0411

Single 10-Bit 65/80 MSPS

A/D Converter

Digital and timing Specifications

AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, Conversion rate: Max specified, 50% clock duty cycle, -1dBFs input signal, 5 pF capacitive

load on data outputs, unless otherwise noted

Parameter

Condition

Min

Typ

Max

Unit

Clock Inputs

Duty Cycle

20

80

% high

Compliance

CMos, LvDs, LvPeCL, sine Wave

Input range

Differential input swing

0.4

vpp

Input range

Differential input swing, sine wave clock input

1.6

vpp

Input common mode

voltage

Keep voltages within ground and voltage of ovDD

0.3

v

ovDD -0.3

v

Input capacitance

Differential

2

pF

Timing

t

PD

start up time from Power Down Mode to Active Mode

900

clock

cycles

t

sLP

start up time from sleep Mode to Active Mode

20

clock

cylcles

t

ovr

out of range recovery time

1

clock

cycles

t

AP

Aperture Delay

0.8

ns

Єrms

Aperture jitter

< 0.5

ps

t

LAt

Pipeline Delay

12

clock

cycles

t

D

output delay (see timing diagram). 5pF load on output bits

3

10

ns

t

DC

output delay relative to CK_eXt (see timing diagram)

1

6

ns

Logic Inputs

v

HI

High Level Input voltage. v

ovDD ≥ 3.0v

2

v

HI

High Level Input voltage. v

ovDD = 1.7v – 3.0v

0.8 ·v

ovDD

v

LI

Low Level Input voltage. v

ovDD ≥ 3.0v

0

0.8

v

LI

Low Level Input voltage. v

ovDD = 1.7v – 3.0v

0

0.2 ·v

ovDD

v

I

HI

High Level Input leakage Current

±10

µA

I

LI

Low Level Input leakage Current

±10

µA

C

I

Input Capacitance

3

pF

Logic Outputs

v

Ho

High Level output voltage

v

ovDD -0.1

v

Lo

Low Level output voltage

0.1

v

C

L

Max capacitive load. Post-driver supply voltage equal to pre-driver

supply voltage v

ovDD = voCvDD

5

pF

C

L

Max capacitive load. Post-driver supply voltage above 2.25v (1)

10

pF

(1) the outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible

to keep dynamic currents and resulting switching noise at a minimum

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