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CY8C28413-24PVXI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C28413-24PVXI Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 78 page  CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Document Number: 001-48111 Rev. *I Page 11 of 78 Pinouts This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations. The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 20-Pin Part Pinout Table 3. 20-Pin Part Pinout (SSOP) Pin No. Type Pin Name Description CY8C28243 20-Pin PSoC Device Digital Analog 1 I/O I, M, S P0[7] Analog column mux and SAR ADC input.[8] 2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. Analog column output.[8, 9] 3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. Analog column output.[8, 9] 4 I/O I, M, S P0[1] Analog column mux and SAR ADC input.[8] 5 Output SMP Switch Mode Pump (SMP) connection to external components. 6 I/O M P1[7] I2C0 Serial Clock (SCL). 7 I/O M P1[5] I2C0 Serial Data (SDA). 8 I/O M P1[3] 9 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[7]. 10 Power VSS Ground connection. 11 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[7]. 12 I/O M P1[2] I2C1 Serial Data (SDA).[10] 13 I/O M P1[4] Optional External Clock Input (EXTCLK). 14 I/O M P1[6] I2C1 Serial Clock (SCL).[10] 15 Input XRES Active high external reset with internal pull-down. 16 I/O I, M, S P0[0] Analog column mux and SAR ADC input.[8] 17 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. Analog column output.[8, 11] 18 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. Analog column output.[8, 11] 19 I/O I, M, S P0[6] Analog column mux and SAR ADC input.[8] 20 Power VDD Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. SSOP 2 1 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] SMP I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss Notes 7. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for CY8C28xxx PSoC devices for details. 8. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. 9. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. 10. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. 11. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. |
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