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SM320F2808-EP Datasheet(PDF) 15 Page - Texas Instruments |
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SM320F2808-EP Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 118 page  www.ti.com SM320F2808-EP, SM320F2806-EP SM320F2801-EP Digital Signal Processors SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007 Table 2-2. Signal Descriptions PIN NO. NAME DESCRIPTION (1) PZ PIN GGM # BALL # JTAG JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active high test pin and must be maintained low at all times during normal device operation. In a low-noise TRST 84 A6 environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board is validated for proper operation of the debugger and the application. (I, ↓) TCK 75 A10 JTAG test clock with internal pullup (I, ↑) JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP TMS 74 B10 controller on the rising edge of TCK. (I, ↑) JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction TDI 73 C9 or data) on a rising edge of TCK. (I, ↑) JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) TDO 76 B9 are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive) Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator EMU0 80 A8 system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive ↑) Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator EMU1 81 B7 system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive, ↑) FLASH VDD3VFL 96 C4 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. TEST1 97 A3 Test Pin. Reserved for Texas Instruments. Must be left unconnected. (I/O) TEST2 98 B3 Test Pin. Reserved for Texas Instruments. Must be left unconnected. (I/O) CLOCK Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0 XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive). External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, XCLKIN 90 B5 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I) Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I) Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2 86 C6 X2. If X2 is not used it must be left unconnected. (O) RESET Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. XRS 78 B8 During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑) The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It is recommended that this pin be driven by an open-drain device. ADC SIGNALS ADCINA7 16 F3 ADC Group A, Channel 7 input (I) ADCINA6 17 F4 ADC Group A, Channel 6 input (I) (1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown Submit Documentation Feedback Introduction 15 |
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