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SM320F2808-EP Datasheet(PDF) 38 Page - Texas Instruments |
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SM320F2808-EP Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 118 page  www.ti.com 3.6.1 OSC and PLL Block X1 XCLKIN (3.3-V clock input) On chip oscillator X2 xor PLLSTS[OSCOFF] OSCCLK PLL VCOCLK 4-bit PLL Select (PLLCR) OSCCLK or VCOCLK CLKIN OSCCLK 0 PLLSTS[PLLOFF] n n ≠ 0 /2 PLLSTS[CLKINDIV] SM320F2808-EP, SM320F2806-EP SM320F2801-EP Digital Signal Processors SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007 The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13. Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers (1) NAME ADDRESS SIZE (x16) DESCRIPTION XCLK 0x7010 1 XCLKOUT Pin Control, X1 and XCLKIN Status Register PLLSTS 0x7011 1 PLL Status Register 0x7012 reserved 8 0x7019 HISPCP 0x701A 1 High-Speed Peripheral Clock Prescaler Register (for HSPCLK) LOSPCP 0x701B 1 Low-Speed Peripheral Clock Prescaler Register (for LSPCLK) PCLKCR0 0x701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x701D 1 Peripheral Clock Control Register 1 LPMCR0 0x701E 1 Low Power Mode Control Register 0 0x701F reserved 1 0x7020 PLLCR 0x7021 1 PLL Control Register SCSR 0x7022 1 System Control and Status Register WDCNTR 0x7023 1 Watchdog Counter Register reserved 0x7024 1 WDKEY 0x7025 1 Watchdog Reset Key Register 0x7026 reserved 3 0x7028 WDCR 0x7029 1 Watchdog Control Register 0x702A reserved 6 0x702F (1) All of the registers in this table are EALLOW protected. Figure 3-8 shows the OSC and PLL block on the 280x. Figure 3-8. OSC and PLL Block Diagram The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following configurations: 1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO. 2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left Functional Overview 38 Submit Documentation Feedback |
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