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MSP430F413IRTDR Datasheet(PDF) 12 Page - Texas Instruments |
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MSP430F413IRTDR Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 64 page  MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 7 654 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 0h ACCVIE NMIIE rw-0 7 654 0 32 1 Address 1h BTIE rw-0 WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE: Oscillator fault interrupt enable NMIIE: Nonmaskable interrupt enable ACCVIE: Flash access violation interrupt enable BTIE: Basic Timer1 interrupt enable interrupt flag register 1 and 2 7 654 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-(0) Address 02h NMIIFG 7 654 0 32 1 Address 3h BTIFG rw-0 WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up, or a reset condition at the RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin BTIFG: Basic Timer1 interrupt flag module enable registers 1 and 2 7 654 0 32 1 Address 04h/05h Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC. rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device. |
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